Merge git://git.denx.de/u-boot into u-boot

[oweals/u-boot.git] / cpu / ppc4xx / traps.c

diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c
index 38b6f89555007a9ac4614a4a88af3599af63d69c..55154b6f0110c262fb264a4e2bcfda7387f0174e 100644 (file)
--- a/cpu/ppc4xx/traps.c
+++ b/cpu/ppc4xx/traps.c
@@ -170,7 +170,7 @@ MachineCheckException(struct pt_regs *regs)
 
        val = get_esr();
 
-#if !defined(CONFIG_440)
+#if !defined(CONFIG_440) && !defined(CONFIG_405EX)
        if (val& ESR_IMCP) {
                printf("Instruction");
                mtspr(ESR, val & ~ESR_IMCP);
@@ -179,7 +179,7 @@ MachineCheckException(struct pt_regs *regs)
        }
        printf(" machine check.\n");
 
-#elif defined(CONFIG_440)
+#elif defined(CONFIG_440) || defined(CONFIG_405EX)
        if (val& ESR_IMCP){
                printf("Instruction Synchronous Machine Check exception\n");
                mtspr(SPRN_ESR, val & ~ESR_IMCP);
@@ -187,10 +187,15 @@ MachineCheckException(struct pt_regs *regs)
                val = mfspr(MCSR);
                if (val & MCSR_IB)
                        printf("Instruction Read PLB Error\n");
+#if defined(CONFIG_440)
                if (val & MCSR_DRB)
                        printf("Data Read PLB Error\n");
                if (val & MCSR_DWB)
                        printf("Data Write PLB Error\n");
+#else
+               if (val & MCSR_DB)
+                       printf("Data PLB Error\n");
+#endif
                if (val & MCSR_TLBP)
                        printf("TLB Parity Error\n");
                if (val & MCSR_ICP){
@@ -209,7 +214,7 @@ MachineCheckException(struct pt_regs *regs)
        }
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
        mfsdram(DDR0_00, val) ;
-       printf("DDR0: DDR0_00 %p\n", val);
+       printf("DDR0: DDR0_00 %lx\n", val);
        val = (val >> 16) & 0xff;
        if (val & 0x80)
                printf("DDR0: At least one interrupt active\n");
@@ -258,44 +263,44 @@ MachineCheckException(struct pt_regs *regs)
                break;
        default:
                mfsdram(DDR0_01, value2);
-               printf("DDR0: No DDR0 error know 0x%x %p\n", val, value2);
+               printf("DDR0: No DDR0 error know 0x%lx %x\n", val, value2);
        }
        mfsdram(DDR0_23, val);
        if (((val >> 16) & 0xff) && corr_ecc)
-               printf("DDR0: Syndrome for correctable ECC event 0x%x\n",
+               printf("DDR0: Syndrome for correctable ECC event 0x%lx\n",
                       (val >> 16) & 0xff);
        mfsdram(DDR0_23, val);
        if (((val >> 8) & 0xff) && uncorr_ecc)
-               printf("DDR0: Syndrome for uncorrectable ECC event 0x%x\n",
+               printf("DDR0: Syndrome for uncorrectable ECC event 0x%lx\n",
                       (val >> 8) & 0xff);
        mfsdram(DDR0_33, val);
        if (val)
                printf("DDR0: Address of command that caused an "
-                      "Out-of-Range interrupt %p\n", val);
+                      "Out-of-Range interrupt %lx\n", val);
        mfsdram(DDR0_34, val);
        if (val && uncorr_ecc)
-               printf("DDR0: Address of uncorrectable ECC event %p\n", val);
+               printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
        mfsdram(DDR0_35, val);
        if (val && uncorr_ecc)
-               printf("DDR0: Address of uncorrectable ECC event %p\n", val);
+               printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
        mfsdram(DDR0_36, val);
        if (val && uncorr_ecc)
-               printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val);
+               printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
        mfsdram(DDR0_37, val);
        if (val && uncorr_ecc)
-               printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val);
+               printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
        mfsdram(DDR0_38, val);
        if (val && corr_ecc)
-               printf("DDR0: Address of correctable ECC event %p\n", val);
+               printf("DDR0: Address of correctable ECC event %lx\n", val);
        mfsdram(DDR0_39, val);
        if (val && corr_ecc)
-               printf("DDR0: Address of correctable ECC event %p\n", val);
+               printf("DDR0: Address of correctable ECC event %lx\n", val);
        mfsdram(DDR0_40, val);
        if (val && corr_ecc)
-               printf("DDR0: Data of correctable ECC event 0x%08x\n", val);
+               printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
        mfsdram(DDR0_41, val);
        if (val && corr_ecc)
-               printf("DDR0: Data of correctable ECC event 0x%08x\n", val);
+               printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
 #endif /* CONFIG_440EPX */
 #endif /* CONFIG_440 */
        show_regs(regs);