Fix PCI-Express on PPC440SPe rev. A.

[oweals/u-boot.git] / cpu / ppc4xx / serial.c

diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c
index 4abd3fc493dc881d5b168f74a216b7c8e9a23ead..3749811dca64a09cd203ac5bce245164a0db3b7a 100644 (file)
--- a/cpu/ppc4xx/serial.c
+++ b/cpu/ppc4xx/serial.c
@@ -59,6 +59,8 @@
 #include <malloc.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*****************************************************************************/
 #ifdef CONFIG_IOP480
 
@@ -161,8 +163,6 @@
 
 int serial_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile char val;
        unsigned short br_reg;
 
@@ -185,8 +185,6 @@ int serial_init (void)
 
 void serial_setbrg (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned short br_reg;
 
        br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
@@ -269,9 +267,19 @@ int serial_tstc ()
 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
 
 #if defined(CONFIG_440)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000300
+#define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000400
+#else
 #define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000200
 #define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000300
-#if defined(CONFIG_440_GX)
+#endif
+
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#define UART2_BASE  CFG_PERIPHERAL_BASE + 0x00000600
+#endif
+
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 #define CR0_MASK        0xdfffffff
 #define CR0_EXTCLK_ENA  0x00800000
 #define CR0_UDIV_POS    0
@@ -279,7 +287,7 @@ int serial_tstc ()
 #define CR0_MASK        0x3fff0000
 #define CR0_EXTCLK_ENA  0x00600000
 #define CR0_UDIV_POS    16
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
 #elif defined(CONFIG_405EP)
 #define UART0_BASE      0xef600300
 #define UART1_BASE      0xef600400
@@ -301,21 +309,25 @@ int serial_tstc ()
 #if defined(CONFIG_UART1_CONSOLE)
 #define ACTING_UART0_BASE      UART1_BASE
 #define ACTING_UART1_BASE      UART0_BASE
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+       defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
+       defined(CONFIG_440SPE)
 #define UART0_SDR           sdr_uart1
 #define UART1_SDR           sdr_uart0
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
 #else
 #define ACTING_UART0_BASE      UART0_BASE
 #define ACTING_UART1_BASE      UART1_BASE
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+       defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
+       defined(CONFIG_440SPE)
 #define UART0_SDR           sdr_uart0
 #define UART1_SDR           sdr_uart1
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
 #endif
 
 #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
-#error "External serial clock not supported on IBM PPC405EP!"
+#error "External serial clock not supported on AMCC PPC405EP!"
 #endif
 
 #define UART_RBR    0x00
@@ -421,8 +433,6 @@ int serial_init_dev (unsigned long dev_base)
 int serial_init(void)
 #endif
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned long reg;
        unsigned long udiv;
        unsigned short bdiv;
@@ -431,7 +441,8 @@ int serial_init(void)
        unsigned long tmp;
 #endif
 
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
+       defined(CONFIG_440SPE)
 #if defined(CONFIG_SERIAL_MULTI)
        if (UART0_BASE == dev_base) {
                mfsdr(UART0_SDR,reg);
@@ -446,7 +457,7 @@ int serial_init(void)
 #endif
 #else
        reg = mfdcr(cntrl0) & ~CR0_MASK;
-#endif /* CONFIG_440_GX */
+#endif /* CONFIG_440GX */
 #ifdef CFG_EXT_SERIAL_CLOCK
        reg |= CR0_EXTCLK_ENA;
        udiv = 1;
@@ -460,7 +471,9 @@ int serial_init(void)
        serial_divs (gd->baudrate, &udiv, &bdiv);
 #endif
 
-#if defined(CONFIG_440_GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+       defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
+       defined(CONFIG_440SPE)
        reg |= udiv << CR0_UDIV_POS;    /* set the UART divisor */
 #if defined(CONFIG_SERIAL_MULTI)
        if (UART0_BASE == dev_base) {
@@ -510,8 +523,6 @@ int serial_init_dev (unsigned long dev_base)
 int serial_init (void)
 #endif
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned long reg;
        unsigned long tmp;
        unsigned long clk;
@@ -587,8 +598,6 @@ void serial_setbrg_dev (unsigned long dev_base)
 void serial_setbrg (void)
 #endif
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned long tmp;
        unsigned long clk;
        unsigned long udiv;
@@ -605,8 +614,28 @@ void serial_setbrg (void)
 #else
        udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
 #endif /* CONFIG_405EP */
+
+#if !defined(CFG_EXT_SERIAL_CLOCK) && \
+       ( defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+         defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
+         defined(CONFIG_440SPE) )
+       serial_divs (gd->baudrate, &udiv, &bdiv);
+       tmp = udiv << CR0_UDIV_POS;             /* set the UART divisor */
+#if defined(CONFIG_SERIAL_MULTI)
+       if (UART0_BASE == dev_base) {
+               mtsdr (UART0_SDR, tmp);
+       } else {
+               mtsdr (UART1_SDR, tmp);
+       }
+#else
+       mtsdr (UART0_SDR, tmp);
+#endif
+
+#else
+
        tmp = gd->baudrate * udiv * 16;
        bdiv = (clk + tmp / 2) / tmp;
+#endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */ 
 
 #if defined(CONFIG_SERIAL_MULTI)
        out8 (dev_base + UART_LCR, 0x80);       /* set DLAB bit */
@@ -870,8 +899,6 @@ int serial_buffered_tstc (void)
 #if (CONFIG_KGDB_SER_INDEX & 2)
 void kgdb_serial_init (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile char val;
        unsigned short br_reg;