ppc4xx: Big cleanup of PPC4xx defines

[oweals/u-boot.git] / cpu / ppc4xx / fdt.c

diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c
index 0323dc52fe59fe7b222326af9dd0176f0db721be..496e0285b5bd802a9445f6df7f0883623d3590a9 100644 (file)
--- a/cpu/ppc4xx/fdt.c
+++ b/cpu/ppc4xx/fdt.c
@@ -37,29 +37,40 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void __ft_board_setup(void *blob, bd_t *bd)
 {
-       u32 val[4];
        int rc;
+       int i;
+       u32 bxcr;
+       u32 ranges[EBC_NUM_BANKS * 4];
+       u32 *p = ranges;
+       char *ebc_path = "/plb/opb/ebc";
 
        ft_cpu_setup(blob, bd);
 
-       /* Fixup NOR mapping */
-       val[0] = 0;                             /* chip select number */
-       val[1] = 0;                             /* always 0 */
-       val[2] = gd->bd->bi_flashstart;
-       val[3] = gd->bd->bi_flashsize;
-       if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0) {
-               rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
-                                         val, sizeof(val), 1);
-       } else {
-               /*
-                * Some 405 PPC's have EBC as direct PLB child in the dts
-                */
-               rc = fdt_find_and_setprop(blob, "/plb/ebc", "ranges",
-                                         val, sizeof(val), 1);
+       /*
+        * Read 4xx EBC bus bridge registers to get mappings of the
+        * peripheral banks into the OPB/PLB address space
+        */
+       for (i = 0; i < EBC_NUM_BANKS; i++) {
+               mtdcr(EBC0_CFGADDR, EBC_BXCR(i));
+               bxcr = mfdcr(EBC0_CFGDATA);
+
+               if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
+                       *p++ = i;
+                       *p++ = 0;
+                       *p++ = bxcr & EBC_BXCR_BAS_MASK;
+                       *p++ = EBC_BXCR_BANK_SIZE(bxcr);
+               }
        }
-       if (rc)
-               printf("Unable to update property NOR mapping, err=%s\n",
+
+       /* Some 405 PPC's have EBC as direct PLB child in the dts */
+       if (fdt_path_offset(blob, "/plb/opb/ebc") < 0)
+               strcpy(ebc_path, "/plb/ebc");
+       rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
+                                 (p - ranges) * sizeof(u32), 1);
+       if (rc) {
+               printf("Unable to update property EBC mappings, err=%s\n",
                       fdt_strerror(rc));
+       }
 }
 void ft_board_setup(void *blob, bd_t *bd) __attribute__((weak, alias("__ft_board_setup")));
 
@@ -102,6 +113,7 @@ void fdt_pcie_setup(void *blob)
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
        sys_info_t sys_info;
+       int off, ndepth = 0;
 
        get_sys_info(&sys_info);
 
@@ -122,15 +134,34 @@ void ft_cpu_setup(void *blob, bd_t *bd)
        fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 
        /*
-        * Setup all baudrates for the UARTs
+        * Fixup all UART clocks for CPU internal UARTs
+        * (only these UARTs are definitely clocked by gd->uart_clk)
+        *
+        * These UARTs are direct childs of /plb/opb. This code
+        * does not touch any UARTs that are connected to the ebc.
         */
-       do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", gd->uart_clk, 1);
+       off = fdt_path_offset(blob, "/plb/opb");
+       while ((off = fdt_next_node(blob, off, &ndepth)) >= 0) {
+               /*
+                * process all sub nodes and stop when we are back
+                * at the starting depth
+                */
+               if (ndepth <= 0)
+                       break;
+
+               /* only update direct childs */
+               if ((ndepth == 1) &&
+                   (fdt_node_check_compatible(blob, off, "ns16550") == 0))
+                       fdt_setprop(blob, off,
+                                   "clock-frequency",
+                                   (void*)&(gd->uart_clk), 4);
+       }
 
        /*
         * Fixup all ethernet nodes
         * Note: aliases in the dts are required for this
         */
-       fdt_fixup_ethernet(blob, bd);
+       fdt_fixup_ethernet(blob);
 
        /*
         * Fixup all available PCIe nodes by setting the device_type property