ppc4xx: Consolidate pci_pre_init() function

[oweals/u-boot.git] / cpu / ppc4xx / fdt.c

diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c
index c55e1cfbb72f94da0838fac7f341ba19d51b3a8c..15a184b5c624cf27ae9c2a2be5e756b3298ace74 100644 (file)
--- a/cpu/ppc4xx/fdt.c
+++ b/cpu/ppc4xx/fdt.c
@@ -42,7 +42,7 @@ void __ft_board_setup(void *blob, bd_t *bd)
        u32 bxcr;
        u32 ranges[EBC_NUM_BANKS * 4];
        u32 *p = ranges;
-       char *ebc_path = "/plb/opb/ebc";
+       char ebc_path[] = "/plb/opb/ebc";
 
        ft_cpu_setup(blob, bd);
 
@@ -51,19 +51,25 @@ void __ft_board_setup(void *blob, bd_t *bd)
         * peripheral banks into the OPB/PLB address space
         */
        for (i = 0; i < EBC_NUM_BANKS; i++) {
-               mtdcr(ebccfga, EBC_BXCR(i));
-               bxcr = mfdcr(ebccfgd);
+               mtdcr(EBC0_CFGADDR, EBC_BXCR(i));
+               bxcr = mfdcr(EBC0_CFGDATA);
 
                if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
                        *p++ = i;
                        *p++ = 0;
                        *p++ = bxcr & EBC_BXCR_BAS_MASK;
                        *p++ = EBC_BXCR_BANK_SIZE(bxcr);
+
+#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
+                       /* Try to update reg property in nor flash node too */
+                       fdt_fixup_nor_flash_size(blob, i,
+                                                EBC_BXCR_BANK_SIZE(bxcr));
+#endif
                }
        }
 
        /* Some 405 PPC's have EBC as direct PLB child in the dts */
-       if (fdt_path_offset(blob, "/plb/opb/ebc") < 0)
+       if (fdt_path_offset(blob, ebc_path) < 0)
                strcpy(ebc_path, "/plb/ebc");
        rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
                                  (p - ranges) * sizeof(u32), 1);
@@ -113,6 +119,7 @@ void fdt_pcie_setup(void *blob)
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
        sys_info_t sys_info;
+       int off, ndepth = 0;
 
        get_sys_info(&sys_info);
 
@@ -133,9 +140,28 @@ void ft_cpu_setup(void *blob, bd_t *bd)
        fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 
        /*
-        * Setup all baudrates for the UARTs
+        * Fixup all UART clocks for CPU internal UARTs
+        * (only these UARTs are definitely clocked by gd->uart_clk)
+        *
+        * These UARTs are direct childs of /plb/opb. This code
+        * does not touch any UARTs that are connected to the ebc.
         */
-       do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", gd->uart_clk, 1);
+       off = fdt_path_offset(blob, "/plb/opb");
+       while ((off = fdt_next_node(blob, off, &ndepth)) >= 0) {
+               /*
+                * process all sub nodes and stop when we are back
+                * at the starting depth
+                */
+               if (ndepth <= 0)
+                       break;
+
+               /* only update direct childs */
+               if ((ndepth == 1) &&
+                   (fdt_node_check_compatible(blob, off, "ns16550") == 0))
+                       fdt_setprop(blob, off,
+                                   "clock-frequency",
+                                   (void*)&(gd->uart_clk), 4);
+       }
 
        /*
         * Fixup all ethernet nodes