Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx

[oweals/u-boot.git] / cpu / ppc4xx / cpu_init.c

diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index 79cfba3a4511d1892c967e012ba5b352b5878a55..66e86372603598a626166dbccc3edc91955e9ddf 100644 (file)
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -25,10 +25,12 @@
 #include <watchdog.h>
 #include <ppc4xx_enet.h>
 #include <asm/processor.h>
+#include <asm/gpio.h>
 #include <ppc4xx.h>
 
-
-#define mtebc(reg, data)  mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
+#if defined(CONFIG_405GP)  || defined(CONFIG_405EP)
+DECLARE_GLOBAL_DATA_PTR;
+#endif
 
 #ifdef CFG_INIT_DCACHE_CS
 # if (CFG_INIT_DCACHE_CS == 0)
@@ -97,7 +99,6 @@
 # endif
 #endif /* CFG_INIT_DCACHE_CS */
 
-
 /*
  * Breath some life into the CPU...
  *
@@ -107,17 +108,27 @@
 void
 cpu_init_f (void)
 {
+#if defined(CONFIG_WATCHDOG)
+       unsigned long val;
+#endif
+
 #if defined(CONFIG_405EP)
        /*
         * GPIO0 setup (select GPIO or alternate function)
         */
-       out32(GPIO0_OSRH, CFG_GPIO0_OSRH);   /* output select */
+#if defined(CFG_GPIO0_OR)
+       out32(GPIO0_OR, CFG_GPIO0_OR);          /* set initial state of output pins     */
+#endif
+#if defined(CFG_GPIO0_ODR)
+       out32(GPIO0_ODR, CFG_GPIO0_ODR);        /* open-drain select                    */
+#endif
+       out32(GPIO0_OSRH, CFG_GPIO0_OSRH);      /* output select                        */
        out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
-       out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
+       out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H);    /* input select                         */
        out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
-       out32(GPIO0_TSRH, CFG_GPIO0_TSRH);   /* three-state select */
+       out32(GPIO0_TSRH, CFG_GPIO0_TSRH);      /* three-state select                   */
        out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
-       out32(GPIO0_TCR, CFG_GPIO0_TCR);     /* enable output driver for outputs */
+       out32(GPIO0_TCR, CFG_GPIO0_TCR);        /* enable output driver for outputs     */
 
        /*
         * Set EMAC noise filter bits
@@ -125,10 +136,17 @@ cpu_init_f (void)
        mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
 #endif /* CONFIG_405EP */
 
+#if defined(CFG_440_GPIO_TABLE)
+       gpio_set_chip_configuration();
+#endif /* CFG_440_GPIO_TABLE */
+
        /*
         * External Bus Controller (EBC) Setup
         */
 #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
+#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
+     defined(CONFIG_405))
        /*
         * Move the next instructions into icache, since these modify the flash
         * we are running from!
@@ -144,6 +162,7 @@ cpu_init_f (void)
        asm volatile("  ori     3, 3, 0xA000"   ::: "r3");
        asm volatile("  mtctr   3"              ::: "ctr");
        asm volatile("2:        bdnz    2b"             ::: "ctr", "cr0");
+#endif
 
        mtebc(pb0ap, CFG_EBC_PB0AP);
        mtebc(pb0cr, CFG_EBC_PB0CR);
@@ -184,14 +203,20 @@ cpu_init_f (void)
        mtebc(pb7cr, CFG_EBC_PB7CR);
 #endif
 
-#if defined(CONFIG_WATCHDOG)
-       unsigned long val;
+#if defined (CFG_EBC_CFG)
+       mtebc(EBC0_CFG, CFG_EBC_CFG);
+#endif
 
+#if defined(CONFIG_WATCHDOG)
        val = mfspr(tcr);
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
        val |= 0xb8000000;      /* generate system reset after 1.34 seconds */
 #else
        val |= 0xf0000000;      /* generate system reset after 2.684 seconds */
+#endif
+#if defined(CFG_4xx_RESET_TYPE)
+       val &= ~0x30000000;                     /* clear WRC bits */
+       val |= CFG_4xx_RESET_TYPE << 28;        /* set board specific WRC type */
 #endif
        mtspr(tcr, val);
 
@@ -209,8 +234,6 @@ cpu_init_f (void)
 int cpu_init_r (void)
 {
 #if defined(CONFIG_405GP)  || defined(CONFIG_405EP)
-       DECLARE_GLOBAL_DATA_PTR;
-
        bd_t *bd = gd->bd;
        unsigned long reg;
 #if defined(CONFIG_405GP)