ppc4xx: Fix 460EX errata with CPU lockup upon high AHB traffic

[oweals/u-boot.git] / cpu / ppc4xx / 4xx_enet.c

diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index d990250fcb3b23e8e05247a871aa03d190159a48..c40e0ca48098bfbf4d22af3214c67efba47b6fcd 100644 (file)
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -274,7 +274,7 @@ static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p)
 static void ppc_4xx_eth_halt (struct eth_device *dev)
 {
        EMAC_4XX_HW_PST hw_p = dev->priv;
-       uint32_t failsafe = 10000;
+       u32 val = 10000;
 
        out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
 
@@ -290,8 +290,8 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
        /* wait for reset */
        while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
                udelay (1000);  /* Delay 1 MS so as not to hammer the register */
-               failsafe--;
-               if (failsafe == 0)
+               val--;
+               if (val == 0)
                        break;
        }
 
@@ -308,6 +308,13 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
        hw_p->print_speed = 1;  /* print speed message again next time */
 #endif
 
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+       /* don't bypass the TAHOE0/TAHOE1 cores for Linux */
+       mfsdr(SDR0_ETH_CFG, val);
+       val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
+       mtsdr(SDR0_ETH_CFG, val);
+#endif
+
        return;
 }
 
@@ -494,11 +501,18 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
        u32 zmiifer;            /* ZMII0_FER reg. */
        u32 rmiifer;            /* RGMII0_FER reg. Bridge 0 */
        u32 rmiifer1;           /* RGMII0_FER reg. Bridge 1 */
+       int mode;
 
        zmiifer  = 0;
        rmiifer  = 0;
        rmiifer1 = 0;
 
+#if defined(CONFIG_460EX)
+       mode = 9;
+#else
+       mode = 10;
+#endif
+
        /* TODO:
         * NOTE: 460GT has 2 RGMII bridge cores:
         *              emac0 ------ RGMII0_BASE
@@ -520,7 +534,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
         * Right now only 2*RGMII is supported. Please extend when needed.
         * sr - 2008-02-19
         */
-       switch (9) {
+       switch (mode) {
        case 1:
                /* 1 MII - 460EX */
                /* GMC0 EMAC4_0, ZMII Bridge */
@@ -703,6 +717,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 #ifdef CONFIG_4xx_DCACHE
        static u32 last_used_ea = 0;
 #endif
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_405EX)
+       int rgmii_channel;
+#endif
 
        EMAC_4XX_HW_PST hw_p = dev->priv;
 
@@ -836,10 +855,12 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
                reg = CONFIG_PHY1_ADDR;
                break;
 #endif
-#if defined (CONFIG_440GX)
+#if defined (CONFIG_PHY2_ADDR)
        case 2:
                reg = CONFIG_PHY2_ADDR;
                break;
+#endif
+#if defined (CONFIG_PHY3_ADDR)
        case 3:
                reg = CONFIG_PHY3_ADDR;
                break;
@@ -1006,12 +1027,17 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
     defined(CONFIG_405EX)
+       if (devnum >= 2)
+               rgmii_channel = devnum - 2;
+       else
+               rgmii_channel = devnum;
+
        if (speed == 1000)
-               reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
+               reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel));
        else if (speed == 100)
-               reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
+               reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel));
        else if (speed == 10)
-               reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
+               reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel));
        else {
                printf("Error in RGMII Speed\n");
                return -1;
@@ -1057,7 +1083,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 #ifdef CONFIG_4xx_DCACHE
                flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
                if (!last_used_ea)
+#if defined(CFG_MEM_TOP_HIDE)
+                       bd_uncached = bis->bi_memsize + CFG_MEM_TOP_HIDE;
+#else
                        bd_uncached = bis->bi_memsize;
+#endif
                else
                        bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
 
@@ -1131,7 +1161,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 #endif
 
 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-               mtdcr (malrxctp8r, hw_p->rx);
+               mtdcr (malrxctp8r, hw_p->rx_phys);
                /* set RX buffer size */
                mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16);
 #else
@@ -1160,6 +1190,26 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
                mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
                break;
 #endif /* CONFIG_440GX */
+#if defined (CONFIG_460GT)
+       case 2:
+               /* setup MAL tx & rx channel pointers */
+               mtdcr (maltxbattr, 0x0);
+               mtdcr (malrxbattr, 0x0);
+               mtdcr (maltxctp2r, hw_p->tx_phys);
+               mtdcr (malrxctp16r, hw_p->rx_phys);
+               /* set RX buffer size */
+               mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16);
+               break;
+       case 3:
+               /* setup MAL tx & rx channel pointers */
+               mtdcr (maltxbattr, 0x0);
+               mtdcr (malrxbattr, 0x0);
+               mtdcr (maltxctp3r, hw_p->tx_phys);
+               mtdcr (malrxctp24r, hw_p->rx_phys);
+               /* set RX buffer size */
+               mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16);
+               break;
+#endif /* CONFIG_460GT */
        case 0:
        default:
                /* setup MAL tx & rx channel pointers */
@@ -1866,14 +1916,22 @@ int ppc_4xx_eth_initialize (bd_t * bis)
                case 2:
                        memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
                               bis->bi_enet2addr, 6);
+#if defined(CONFIG_460GT)
+                       hw_addr[eth_num] = 0x300;
+#else
                        hw_addr[eth_num] = 0x400;
+#endif
                        break;
 #endif
 #ifdef CONFIG_HAS_ETH3
                case 3:
                        memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
                               bis->bi_enet3addr, 6);
+#if defined(CONFIG_460GT)
+                       hw_addr[eth_num] = 0x400;
+#else
                        hw_addr[eth_num] = 0x600;
+#endif
                        break;
 #endif
                }