Fix ppc4xx clear_bss() code

[oweals/u-boot.git] / cpu / ppc4xx / 44x_spd_ddr2.c

diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 18b90ba5ac630b14a35f1ef7ab05f0b0535b9cc6..e19929437e2d4d0c389ada193fa64274da40c6be 100644 (file)
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -120,10 +120,10 @@
  * memory.
  *
  * If at some time this restriction doesn't apply anymore, just define
- * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
+ * CONFIG_4xx_DCACHE in the board config file and this code should setup
  * everything correctly.
  */
-#ifdef CFG_ENABLE_SDRAM_CACHE
+#ifdef CONFIG_4xx_DCACHE
 #define MY_TLB_WORD2_I_ENABLE  0                       /* enable caching on SDRAM */
 #else
 #define MY_TLB_WORD2_I_ENABLE  TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
@@ -621,10 +621,9 @@ static void get_spd_info(unsigned long *dimm_populated,
        }
 }
 
-#ifdef CONFIG_ADD_RAM_INFO
 void board_add_ram_info(int use_default)
 {
-       PPC440_SYS_INFO board_cfg;
+       PPC4xx_SYS_INFO board_cfg;
        u32 val;
 
        if (is_ecc_enabled())
@@ -642,7 +641,6 @@ void board_add_ram_info(int use_default)
        val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
        printf(", CL%d)", val);
 }
-#endif
 
 /*------------------------------------------------------------------
  * For the memory DIMMs installed, this routine verifies that they
@@ -743,7 +741,7 @@ static void check_frequency(unsigned long *dimm_populated,
        unsigned long calc_cycle_time;
        unsigned long sdram_freq;
        unsigned long sdr_ddrpll;
-       PPC440_SYS_INFO board_cfg;
+       PPC4xx_SYS_INFO board_cfg;
 
        /*------------------------------------------------------------------
         * Get the board configuration info.
@@ -1355,7 +1353,7 @@ static void program_mode(unsigned long *dimm_populated,
        unsigned long max_4_0_tcyc_ns_x_100;
        unsigned long max_5_0_tcyc_ns_x_100;
        unsigned long cycle_time_ns_x_100[3];
-       PPC440_SYS_INFO board_cfg;
+       PPC4xx_SYS_INFO board_cfg;
        unsigned char cas_2_0_available;
        unsigned char cas_2_5_available;
        unsigned char cas_3_0_available;
@@ -1642,7 +1640,7 @@ static void program_rtr(unsigned long *dimm_populated,
                        unsigned char *iic0_dimm_addr,
                        unsigned long num_dimm_banks)
 {
-       PPC440_SYS_INFO board_cfg;
+       PPC4xx_SYS_INFO board_cfg;
        unsigned long max_refresh_rate;
        unsigned long dimm_num;
        unsigned long refresh_rate_type;
@@ -1739,7 +1737,7 @@ static void program_tr(unsigned long *dimm_populated,
        unsigned long sdram_freq;
        unsigned long sdr_ddrpll;
 
-       PPC440_SYS_INFO board_cfg;
+       PPC4xx_SYS_INFO board_cfg;
 
        /*------------------------------------------------------------------
         * Get the board configuration info.
@@ -2050,14 +2048,10 @@ static void program_bxcf(unsigned long *dimm_populated,
        /*------------------------------------------------------------------
         * Set the BxCF regs.  First, wipe out the bank config registers.
         *-----------------------------------------------------------------*/
-       mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF);
-       mtdcr(SDRAMC_CFGDATA, 0x00000000);
-       mtdcr(SDRAMC_CFGADDR, SDRAM_MB1CF);
-       mtdcr(SDRAMC_CFGDATA, 0x00000000);
-       mtdcr(SDRAMC_CFGADDR, SDRAM_MB2CF);
-       mtdcr(SDRAMC_CFGDATA, 0x00000000);
-       mtdcr(SDRAMC_CFGADDR, SDRAM_MB3CF);
-       mtdcr(SDRAMC_CFGDATA, 0x00000000);
+       mtsdram(SDRAM_MB0CF, 0x00000000);
+       mtsdram(SDRAM_MB1CF, 0x00000000);
+       mtsdram(SDRAM_MB2CF, 0x00000000);
+       mtsdram(SDRAM_MB3CF, 0x00000000);
 
        mode = SDRAM_BXCF_M_BE_ENABLE;
 
@@ -2109,8 +2103,9 @@ static void program_bxcf(unsigned long *dimm_populated,
                                bank_0_populated = 1;
 
                        for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
-                               mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF + ((dimm_num + bank_0_populated + ind_rank) << 2));
-                               mtdcr(SDRAMC_CFGDATA, mode);
+                               mtsdram(SDRAM_MB0CF +
+                                       ((dimm_num + bank_0_populated + ind_rank) << 2),
+                                       mode);
                        }
                }
        }