PPC4xx: Minimal changes to add vxWorks support

[oweals/u-boot.git] / cpu / ppc4xx / 44x_spd_ddr.c

diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c
index fe7bbabd596d2360e619d46bca5b92c6759448a9..b9cf5cbfccaf0b8ebdfa4a32616c2ebd3674cbae 100644 (file)
--- a/cpu/ppc4xx/44x_spd_ddr.c
+++ b/cpu/ppc4xx/44x_spd_ddr.c
@@ -70,6 +70,15 @@
 
 #define ONE_BILLION    1000000000
 
+/*
+ * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
+ */
+void __spd_ddr_init_hang (void)
+{
+       hang ();
+}
+void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
+
 /*-----------------------------------------------------------------------------
   |  Memory Controller Options 0
   +-----------------------------------------------------------------------------*/
@@ -242,10 +251,10 @@
  * memory.
  *
  * If at some time this restriction doesn't apply anymore, just define
- * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
+ * CONFIG_4xx_DCACHE in the board config file and this code should setup
  * everything correctly.
  */
-#ifdef CFG_ENABLE_SDRAM_CACHE
+#ifdef CONFIG_4xx_DCACHE
 #define MY_TLB_WORD2_I_ENABLE  0                       /* enable caching on SDRAM */
 #else
 #define MY_TLB_WORD2_I_ENABLE  TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
@@ -260,9 +269,8 @@ struct bank_param {
 typedef struct bank_param BANKPARMS;
 
 #ifdef CFG_SIMULATE_SPD_EEPROM
-extern unsigned char cfg_simulate_spd_eeprom[128];
+extern const unsigned char cfg_simulate_spd_eeprom[128];
 #endif
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
 
 static unsigned char spd_read(uchar chip, uint addr);
 static void get_spd_info(unsigned long *dimm_populated,
@@ -337,7 +345,7 @@ long int spd_sdram(void) {
         */
        check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
        /*
         * Soft-reset SDRAM controller.
         */
@@ -467,7 +475,7 @@ static void get_spd_info(unsigned long *dimm_populated,
 
        if (dimm_found == FALSE) {
                printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
-               hang();
+               spd_ddr_init_hang ();
        }
 }
 
@@ -490,7 +498,7 @@ static void check_mem_type(unsigned long *dimm_populated,
                                       dimm_num);
                                printf("Only DDR SDRAM DIMMs are supported.\n");
                                printf("Replace the DIMM module with a supported DIMM.\n\n");
-                               hang();
+                               spd_ddr_init_hang ();
                                break;
                        }
                }
@@ -510,7 +518,7 @@ static void check_volt_type(unsigned long *dimm_populated,
                        if (voltage_type != 0x04) {
                                printf("ERROR: DIMM %lu with unsupported voltage level.\n",
                                       dimm_num);
-                               hang();
+                               spd_ddr_init_hang ();
                        } else {
                                debug("DIMM %lu voltage level supported.\n", dimm_num);
                        }
@@ -581,7 +589,7 @@ static void program_cfg0(unsigned long *dimm_populated,
                                printf("WARNING: DIMM with datawidth of %lu bits.\n",
                                       data_width);
                                printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
-                               hang();
+                               spd_ddr_init_hang ();
                        }
                        break;
                }
@@ -637,7 +645,7 @@ static void program_rtr(unsigned long *dimm_populated,
        unsigned char refresh_rate_type;
        unsigned long refresh_interval;
        unsigned long sdram_rtr;
-       PPC440_SYS_INFO sys_info;
+       PPC4xx_SYS_INFO sys_info;
 
        /*
         * get the board info
@@ -713,7 +721,7 @@ static void program_tr0(unsigned long *dimm_populated,
        unsigned long tcyc_2_0_ns_x_10;
        unsigned long tcyc_reg;
        unsigned long bus_period_x_10;
-       PPC440_SYS_INFO sys_info;
+       PPC4xx_SYS_INFO sys_info;
        unsigned long residue;
 
        /*
@@ -769,7 +777,7 @@ static void program_tr0(unsigned long *dimm_populated,
                                if ((tcyc_reg & 0x0F) >= 10) {
                                        printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
                                               dimm_num);
-                                       hang();
+                                       spd_ddr_init_hang ();
                                }
 
                                cycle_time_ns_x_10[cas_index] =
@@ -849,7 +857,7 @@ static void program_tr0(unsigned long *dimm_populated,
                printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
                printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
                printf("Make sure the PLB speed is within the supported range.\n");
-               hang();
+               spd_ddr_init_hang ();
        }
 
        /*
@@ -1008,6 +1016,7 @@ static int short_mem_test(void)
                         */
                        for (i = 0; i < NUMMEMTESTS; i++) {
                                for (j = 0; j < NUMMEMWORDS; j++) {
+                                       /* printf("bank enabled base:%x\n", &membase[j]); */
                                        membase[j] = test[i][j];
                                        ppcDcbf((unsigned long)&(membase[j]));
                                }
@@ -1056,7 +1065,7 @@ static void program_tr1(void)
        unsigned char window_found;
        unsigned char fail_found;
        unsigned char pass_found;
-       PPC440_SYS_INFO sys_info;
+       PPC4xx_SYS_INFO sys_info;
 
        /*
         * get the board info
@@ -1160,7 +1169,7 @@ static void program_tr1(void)
         */
        if (window_found == FALSE) {
                printf("ERROR: Cannot determine a common read delay.\n");
-               hang();
+               spd_ddr_init_hang ();
        }
 
        /*
@@ -1188,9 +1197,6 @@ static void program_tr1(void)
        }
 
        rdclt_average = ((max_start + max_end) >> 1);
-       if (rdclt_average >= 0x60)
-               while (1)
-                       ;
 
        if (rdclt_average < 0) {
                rdclt_average = 0;
@@ -1310,7 +1316,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
                                printf("ERROR: Unsupported value for the banksize: %d.\n",
                                       bank_size_id);
                                printf("Replace the DIMM module with a supported DIMM.\n\n");
-                               hang();
+                               spd_ddr_init_hang ();
                        }
 
                        switch (num_col_addr) {
@@ -1332,7 +1338,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
                                printf("ERROR: Unsupported value for number of "
                                       "column addresses: %d.\n", num_col_addr);
                                printf("Replace the DIMM module with a supported DIMM.\n\n");
-                               hang();
+                               spd_ddr_init_hang ();
                        }
 
                        /*
@@ -1340,14 +1346,14 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
                         */
                        cr |= SDRAM_BXCR_SDBE;
 
-                       for (i = 0; i < num_banks; i++) {
+                       for (i = 0; i < num_banks; i++) {
                                bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
                                        (4 << 20) * bank_size_id;
                                bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
                                debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n",
                                      dimm_num, i, ctrl_bank_num[dimm_num]+i,
                                      bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes);
-                       }
+                       }
                }
        }