Merge with /home/sr/git/u-boot

[oweals/u-boot.git] / cpu / ppc4xx / 405gp_pci.c

diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index fa5acfc0de6cea6b660fca5633596c70fb727446..ebbcfd573ac9bfc7518c4d22b9f5747f807844b1 100644 (file)
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -95,9 +95,10 @@ void pci_405gp_init(struct pci_controller *hose)
 
        unsigned short temp_short;
        unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
-#if defined(CONFIG_CPCI405)
+#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
        unsigned long ptmla[2]    = {bd->bi_memstart, bd->bi_flashstart};
        unsigned long ptmms[2]    = {~(bd->bi_memsize - 1) | 1, ~(bd->bi_flashsize - 1) | 1};
+       char *ptmla_str, *ptmms_str;
 #else
        unsigned long ptmla[2]    = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
        unsigned long ptmms[2]    = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
@@ -113,6 +114,27 @@ void pci_405gp_init(struct pci_controller *hose)
        unsigned long pmmpcila[3] = {0x80000000, 0,0};
        unsigned long pmmpciha[3] = {0x00000000, 0,0};
 #endif
+#ifdef CONFIG_PCI_PNP
+#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
+       char *s;
+#endif
+#endif
+
+#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
+       ptmla_str = getenv("ptm1la");
+       ptmms_str = getenv("ptm1ms");
+       if(NULL != ptmla_str && NULL != ptmms_str ) {
+               ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
+               ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
+       }
+
+       ptmla_str = getenv("ptm2la");
+       ptmms_str = getenv("ptm2ms");
+       if(NULL != ptmla_str && NULL != ptmms_str ) {
+               ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
+               ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
+       }
+#endif
 
        /*
         * Register the hose
@@ -206,11 +228,14 @@ void pci_405gp_init(struct pci_controller *hose)
         *--------------------------------------------------------------------------*/
        out32r(PTM1LA,    ptmla[0]);         /* insert address                     */
        out32r(PTM1MS,    ptmms[0]);         /* insert size, enable bit is 1       */
+       pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
 
        /*--------------------------------------------------------------------------+
         * 405GP PCI Target configuration.  (PTM2)
         *--------------------------------------------------------------------------*/
        out32r(PTM2LA, ptmla[1]);            /* insert address                     */
+       pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
+
        if (ptmms[1] == 0)
        {
                out32r(PTM2MS,    0x00000001);   /* set enable bit                     */
@@ -251,8 +276,9 @@ void pci_405gp_init(struct pci_controller *hose)
        }
 
 #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
-#if (CONFIG_PCI_HOSE == PCI_HOST_AUTO)
-       if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
+#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
+       if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
+           (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
 #endif
        {
                /*--------------------------------------------------------------------------+
@@ -281,7 +307,8 @@ void pci_405gp_init(struct pci_controller *hose)
         * Scan the PCI bus and configure devices found.
         *--------------------------------------------------------------------------*/
 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
-       if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
+       if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
+           (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
 #endif
        {
 #ifdef CONFIG_PCI_SCAN_SHOW
@@ -361,7 +388,7 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
  */
 static struct pci_config_table pci_405gp_config_table[] = {
 /*if VendID is 0 it terminates the table search (ie Walnut)*/
-#if CFG_PCI_SUBSYS_VENDORID
+#ifdef CFG_PCI_SUBSYS_VENDORID
        {CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
         PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
 #endif
@@ -408,15 +435,23 @@ void pci_440_init (struct pci_controller *hose)
 
        /*--------------------------------------------------------------------------+
         * The PCI initialization sequence enable bit must be set ... if not abort
-     * pci setup since updating the bit requires chip reset.
+        * pci setup since updating the bit requires chip reset.
         *--------------------------------------------------------------------------*/
-    strap = mfdcr(cpc0_strp1);
-    if( (strap & 0x00040000) == 0 ){
-       printf("PCI: CPC0_STRP1[PISE] not set.\n");
-       printf("PCI: Configuration aborted.\n");
-       return;
-    }
-
+#if defined (CONFIG_440_GX) || defined (CONFIG_440_EP) || defined(CONFIG_440_GR)
+       mfsdr(sdr_sdstp1,strap);
+       if ( (strap & 0x00010000) == 0 ){
+               printf("PCI: SDR0_STRP1[PISE] not set.\n");
+               printf("PCI: Configuration aborted.\n");
+               return;
+       }
+#else
+       strap = mfdcr(cpc0_strp1);
+       if( (strap & 0x00040000) == 0 ){
+               printf("PCI: CPC0_STRP1[PISE] not set.\n");
+               printf("PCI: Configuration aborted.\n");
+               return;
+       }
+#endif
        /*--------------------------------------------------------------------------+
         * PCI controller init
         *--------------------------------------------------------------------------*/
@@ -460,8 +495,13 @@ void pci_440_init (struct pci_controller *hose)
     out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
 #endif
 
-    out32r( PCIX0_BRDGOPT1, 0x10000060 );               /* PLB Rq pri highest   */
-    out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config   */
+#if defined(CONFIG_440_GX)
+       out32r( PCIX0_BRDGOPT1, 0x04000060 );               /* PLB Rq pri highest   */
+       out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1  */
+#elif defined(PCIX0_BRDGOPT1)
+       out32r( PCIX0_BRDGOPT1, 0x10000060 );               /* PLB Rq pri highest   */
+       out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config   */
+#endif
 
        /*--------------------------------------------------------------------------+
         * PCI master init: default is one 256MB region for PCI memory:
@@ -491,7 +531,9 @@ void pci_440_init (struct pci_controller *hose)
 #ifdef CONFIG_PCI_SCAN_SHOW
        printf("PCI:   Bus Dev VenId DevId Class Int\n");
 #endif
+#if !defined(CONFIG_440_EP) && !defined(CONFIG_440_GR)
        out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
+#endif
        hose->last_busno = pci_hose_scan(hose);
     }
 }