ppc4xx: Consolidate pci_master_init() function

[oweals/u-boot.git] / cpu / nios2 / start.S

diff --git a/cpu/nios2/start.S b/cpu/nios2/start.S
index 4c6e47066a3c770a7c1bc5ee26ee2627c1feddf8..31cd5b004a0502d4ef38e6faa0ab3c4f86162aa0 100644 (file)
--- a/cpu/nios2/start.S
+++ b/cpu/nios2/start.S
@@ -23,6 +23,7 @@
 
 
 #include <config.h>
+#include <timestamp.h>
 #include <version.h>
 
 /*************************************************************************
@@ -39,9 +40,9 @@ _start:
         * just be invalidating the cache a second time. If cache
         * is not implemented initi behaves as nop.
         */
-       ori     r4, r0, %lo(CFG_ICACHELINE_SIZE)
-       movhi   r5, %hi(CFG_ICACHE_SIZE)
-       ori     r5, r5, %lo(CFG_ICACHE_SIZE)
+       ori     r4, r0, %lo(CONFIG_SYS_ICACHELINE_SIZE)
+       movhi   r5, %hi(CONFIG_SYS_ICACHE_SIZE)
+       ori     r5, r5, %lo(CONFIG_SYS_ICACHE_SIZE)
        mov     r6, r0
 0:     initi   r6
        add     r6, r6, r4
@@ -67,10 +68,10 @@ _except_end:
        /* DCACHE INIT -- if dcache not implemented, initd behaves as
         * nop.
         */
-       movhi   r4, %hi(CFG_DCACHELINE_SIZE)
-       ori     r4, r4, %lo(CFG_DCACHELINE_SIZE)
-       movhi   r5, %hi(CFG_DCACHE_SIZE)
-       ori     r5, r5, %lo(CFG_DCACHE_SIZE)
+       movhi   r4, %hi(CONFIG_SYS_DCACHELINE_SIZE)
+       ori     r4, r4, %lo(CONFIG_SYS_DCACHELINE_SIZE)
+       movhi   r5, %hi(CONFIG_SYS_DCACHE_SIZE)
+       ori     r5, r5, %lo(CONFIG_SYS_DCACHE_SIZE)
        mov     r6, r0
 1:     initd   0(r6)
        add     r6, r6, r4
@@ -136,8 +137,8 @@ _reloc:
        ori     r4, r4, %lo(_except_start)
        movhi   r5, %hi(_except_end)
        ori     r5, r5, %lo(_except_end)
-       movhi   r6, %hi(CFG_EXCEPTION_ADDR)
-       ori     r6, r6, %lo(CFG_EXCEPTION_ADDR)
+       movhi   r6, %hi(CONFIG_SYS_EXCEPTION_ADDR)
+       ori     r6, r6, %lo(CONFIG_SYS_EXCEPTION_ADDR)
        beq     r4, r6, 7f      /* Skip if at proper addr */
 
 6:     ldwio   r7, 0(r4)
@@ -150,8 +151,8 @@ _reloc:
 
        /* STACK INIT -- zero top two words for call back chain.
         */
-       movhi   sp, %hi(CFG_INIT_SP)
-       ori     sp, sp, %lo(CFG_INIT_SP)
+       movhi   sp, %hi(CONFIG_SYS_INIT_SP)
+       ori     sp, sp, %lo(CONFIG_SYS_INIT_SP)
        addi    sp, sp, -8
        stw     r0, 0(sp)
        stw     r0, 4(sp)
@@ -178,24 +179,24 @@ _reloc:
  * Instruction performance varies based on the core. For cores
  * with icache and static/dynamic branch prediction (II/f, II/s):
  *
- *     Normal ALU (e.g. add, cmp, etc):        1 cycle
- *     Branch (correctly predicted, taken):    2 cycles
+ *     Normal ALU (e.g. add, cmp, etc):        1 cycle
+ *     Branch (correctly predicted, taken):    2 cycles
  *     Negative offset is predicted (II/s).
  *
  * For cores without icache and no branch prediction (II/e):
  *
- *     Normal ALU (e.g. add, cmp, etc):        6 cycles
- *     Branch (no prediction):                 6 cycles
+ *     Normal ALU (e.g. add, cmp, etc):        6 cycles
+ *     Branch (no prediction):                 6 cycles
  *
  * For simplicity, if an instruction cache is implemented we
  * assume II/f or II/s. Otherwise, we use the II/e.
  *
  */
-       .globl dly_clks
+       .globl dly_clks
 
 dly_clks:
 
-#if (CFG_ICACHE_SIZE > 0)
+#if (CONFIG_SYS_ICACHE_SIZE > 0)
        subi    r4, r4, 3               /* 3 clocks/loop        */
 #else
        subi    r4, r4, 12              /* 12 clocks/loop       */
@@ -212,5 +213,5 @@ dly_clks:
 
 version_string:
        .ascii U_BOOT_VERSION
-       .ascii " (", __DATE__, " - ", __TIME__, ")"
+       .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
        .ascii CONFIG_IDENT_STRING, "\0"