#endif /* CONFIG_8xx_CONS_SCCx */
+#if !defined(CONFIG_SYS_SMC_RXBUFLEN)
+#define CONFIG_SYS_SMC_RXBUFLEN 1
+#define CONFIG_SYS_MAXIDLE 0
+#else
+#if !defined(CONFIG_SYS_MAXIDLE)
+#error "you must define CONFIG_SYS_MAXIDLE"
+#endif
+#endif
+
+typedef volatile struct serialbuffer {
+ cbd_t rxbd; /* Rx BD */
+ cbd_t txbd; /* Tx BD */
+ uint rxindex; /* index for next character to read */
+ volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
+ volatile uchar txbuf; /* tx buffers */
+} serialbuffer_t;
+
static void serial_setdivisor(volatile cpm8xx_t *cp)
{
int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile smc_t *sp;
volatile smc_uart_t *up;
- volatile cbd_t *tbdf, *rbdf;
volatile cpm8xx_t *cp = &(im->im_cpm);
#if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
#endif
uint dpaddr;
+ volatile serialbuffer_t *rtx;
/* initialize pointers to SMC */
up->smc_rpbase = 0;
#endif
- /* Disable transmitter/receiver.
- */
+ /* Disable transmitter/receiver. */
sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
- /* Enable SDMA.
- */
+ /* Enable SDMA. */
im->im_siu_conf.sc_sdcr = 1;
/* clear error conditions */
#endif
#if defined(CONFIG_8xx_CONS_SMC1)
- /* Use Port B for SMC1 instead of other functions.
- */
+ /* Use Port B for SMC1 instead of other functions. */
cp->cp_pbpar |= 0x000000c0;
cp->cp_pbdir &= ~0x000000c0;
cp->cp_pbodr &= ~0x000000c0;
#else /* CONFIG_8xx_CONS_SMC2 */
# if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
- /* Use Port A for SMC2 instead of other functions.
- */
+ /* Use Port A for SMC2 instead of other functions. */
ip->iop_papar |= 0x00c0;
ip->iop_padir &= ~0x00c0;
ip->iop_paodr &= ~0x00c0;
# else /* must be a 860 then */
/* Use Port B for SMC2 instead of other functions.
- */
+ */
cp->cp_pbpar |= 0x00000c00;
cp->cp_pbdir &= ~0x00000c00;
cp->cp_pbodr &= ~0x00000c00;
*/
#ifdef CONFIG_SYS_ALLOC_DPRAM
- dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
+ /* allocate
+ * size of struct serialbuffer with bd rx/tx, buffer rx/tx and rx index
+ */
+ dpaddr = dpram_alloc_align((sizeof(serialbuffer_t)), 8);
#else
dpaddr = CPM_SERIAL_BASE ;
#endif
+ rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr];
/* Allocate space for two buffer descriptors in the DP ram.
* For now, this address seems OK, but it may have to
* change with newer versions of the firmware.
* damm: allocating space after the two buffers for rx/tx data
*/
- rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
- rbdf->cbd_bufaddr = (uint) (rbdf+2);
- rbdf->cbd_sc = 0;
- tbdf = rbdf + 1;
- tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
- tbdf->cbd_sc = 0;
+ rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
+ rtx->rxbd.cbd_sc = 0;
- /* Set up the uart parameters in the parameter ram.
- */
+ rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
+ rtx->txbd.cbd_sc = 0;
+
+ /* Set up the uart parameters in the parameter ram. */
up->smc_rbase = dpaddr;
up->smc_tbase = dpaddr+sizeof(cbd_t);
up->smc_rfcr = SMC_EB;
smc_setbrg ();
#endif
- /* Make the first buffer the only buffer.
- */
- tbdf->cbd_sc |= BD_SC_WRAP;
- rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
+ /* Make the first buffer the only buffer. */
+ rtx->txbd.cbd_sc |= BD_SC_WRAP;
+ rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
- /* Single character receive.
- */
- up->smc_mrblr = 1;
- up->smc_maxidl = 0;
-
- /* Initialize Tx/Rx parameters.
- */
+ /* single/multi character receive. */
+ up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
+ up->smc_maxidl = CONFIG_SYS_MAXIDLE;
+ rtx->rxindex = 0;
+ /* Initialize Tx/Rx parameters. */
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
- /* Enable transmitter/receiver.
- */
+ /* Enable transmitter/receiver. */
sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
return (0);
static void
smc_putc(const char c)
{
- volatile cbd_t *tbdf;
- volatile char *buf;
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
+ volatile serialbuffer_t *rtx;
#ifdef CONFIG_MODEM_SUPPORT
if (gd->be_quiet)
up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
#endif
- tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
-
- /* Wait for last character to go.
- */
-
- buf = (char *)tbdf->cbd_bufaddr;
+ rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
- *buf = c;
- tbdf->cbd_datlen = 1;
- tbdf->cbd_sc |= BD_SC_READY;
+ /* Wait for last character to go. */
+ rtx->txbuf = c;
+ rtx->txbd.cbd_datlen = 1;
+ rtx->txbd.cbd_sc |= BD_SC_READY;
__asm__("eieio");
- while (tbdf->cbd_sc & BD_SC_READY) {
+ while (rtx->txbd.cbd_sc & BD_SC_READY) {
WATCHDOG_RESET ();
__asm__("eieio");
}
static int
smc_getc(void)
{
- volatile cbd_t *rbdf;
- volatile unsigned char *buf;
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
- unsigned char c;
+ volatile serialbuffer_t *rtx;
+ unsigned char c;
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
#ifdef CONFIG_SYS_SMC_UCODE_PATCH
up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
#endif
+ rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
- rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
-
- /* Wait for character to show up.
- */
- buf = (unsigned char *)rbdf->cbd_bufaddr;
-
- while (rbdf->cbd_sc & BD_SC_EMPTY)
+ /* Wait for character to show up. */
+ while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
WATCHDOG_RESET ();
- c = *buf;
- rbdf->cbd_sc |= BD_SC_EMPTY;
+ /* the characters are read one by one,
+ * use the rxindex to know the next char to deliver
+ */
+ c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex);
+ rtx->rxindex++;
+ /* check if all char are readout, then make prepare for next receive */
+ if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
+ rtx->rxindex = 0;
+ rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
+ }
return(c);
}
static int
smc_tstc(void)
{
- volatile cbd_t *rbdf;
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
+ volatile serialbuffer_t *rtx;
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
#ifdef CONFIG_SYS_SMC_UCODE_PATCH
up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
#endif
- rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
+ rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
- return(!(rbdf->cbd_sc & BD_SC_EMPTY));
+ return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
}
struct serial_device serial_smc_device =
}
#endif /* CONFIG_LWMON */
- /* Disable transmitter/receiver.
- */
+ /* Disable transmitter/receiver. */
sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
#if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
ip->iop_pdpar |= ((3 << (2 * SCC_INDEX)));
#endif
- /* Allocate space for two buffer descriptors in the DP ram.
- */
+ /* Allocate space for two buffer descriptors in the DP ram. */
#ifdef CONFIG_SYS_ALLOC_DPRAM
dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
dpaddr = CPM_SERIAL2_BASE ;
#endif
- /* Enable SDMA.
- */
+ /* Enable SDMA. */
im->im_siu_conf.sc_sdcr = 0x0001;
/* Set the physical address of the host memory buffers in
tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
tbdf->cbd_sc = 0;
- /* Set up the baud rate generator.
- */
+ /* Set up the baud rate generator. */
scc_setbrg ();
- /* Set up the uart parameters in the parameter ram.
- */
+ /* Set up the uart parameters in the parameter ram. */
up->scc_genscc.scc_rbase = dpaddr;
up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
- /* Initialize Tx/Rx parameters.
- */
+ /* Initialize Tx/Rx parameters. */
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
up->scc_char8 = 0x8000;
up->scc_rccm = 0xc0ff;
- /* Set low latency / small fifo.
- */
+ /* Set low latency / small fifo. */
sp->scc_gsmrh = SCC_GSMRH_RFW;
/* Set SCC(x) clock mode to 16x
* Wire BRG1 to SCCn
*/
- /* Set UART mode, clock divider 16 on Tx and Rx
- */
+ /* Set UART mode, clock divider 16 on Tx and Rx */
sp->scc_gsmrl &= ~0xF;
sp->scc_gsmrl |=
(SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
sp->scc_psmr = 0;
sp->scc_psmr |= SCU_PSMR_CL;
- /* Mask all interrupts and remove anything pending.
- */
+ /* Mask all interrupts and remove anything pending. */
sp->scc_sccm = 0;
sp->scc_scce = 0xffff;
sp->scc_dsr = 0x7e7e;
sp->scc_psmr = 0x3000;
- /* Make the first buffer the only buffer.
- */
+ /* Make the first buffer the only buffer. */
tbdf->cbd_sc |= BD_SC_WRAP;
rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
- /* Enable transmitter/receiver.
- */
+ /* Enable transmitter/receiver. */
sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
return (0);
tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
- /* Wait for last character to go.
- */
+ /* Wait for last character to go. */
buf = (char *)tbdf->cbd_bufaddr;
rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
- /* Wait for character to show up.
- */
+ /* Wait for character to show up. */
buf = (unsigned char *)rbdf->cbd_bufaddr;
while (rbdf->cbd_sc & BD_SC_EMPTY)