Copy Global Data Pointer to r29 for DECLARE_GLOBAL_DATA_PTR

[oweals/u-boot.git] / cpu / mpc86xx / start.S

diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index b96363151d88d6e581c5121d605697916fad521d..25687f8bb7538f2df04b45d4de4ab4d473c16b37 100644 (file)
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -207,11 +207,7 @@ boot_warm:
        /* init the L2 cache */
        addis   r3, r0, L2_INIT@h
        ori     r3, r3, L2_INIT@l
-       sync
        mtspr   l2cr, r3        
-#ifdef CONFIG_ALTIVEC
-       dssall
-#endif
        /* invalidate the L2 cache */
        bl      l2cache_invalidate
        sync
@@ -245,6 +241,13 @@ in_flash:
        bl      setup_ccsrbar
 #endif
        
+       /* Fix for SMP linux - Changing arbitration to round-robin */
+       lis     r3, CFG_CCSRBAR@h
+       ori     r3, r3, 0x1000
+       xor     r4, r4, r4
+       li      r4, 0x1000
+       stw     r4, 0(r3)
+
        /* setup the law entries */
        bl      law_entry
        sync
@@ -280,9 +283,9 @@ in_flash:
        /* make sure timer enabled in guts register too */
        lis     r3, CFG_CCSRBAR@h
        oris    r3,r3, 0xE
-       ori     r3,r3,0x0070  /*Jason from 3*/
+       ori     r3,r3,0x0070
        lwz     r4, 0(r3)
-       lis     r5,0xFFFC     /*Jason from 0xffff*/
+       lis     r5,0xFFFC
        ori     r5,r5,0x5FFF
        and     r4,r4,r5
        stw     r4,0(r3)
@@ -811,8 +814,9 @@ relocate_code:
 
         mr     r1,  r3         /* Set new stack pointer                */
        mr      r9,  r4         /* Save copy of Global Data pointer     */
+       mr      r29, r9         /* Save for DECLARE_GLOBAL_DATA_PTR     */
        mr      r10, r5         /* Save copy of Destination Address     */
-        
+
        mr      r3,  r5                         /* Destination Address  */
        lis     r4, CFG_MONITOR_BASE@h          /* Source      Address  */
        ori     r4, r4, CFG_MONITOR_BASE@l
@@ -1193,13 +1197,6 @@ secondary_cpu_setup:
        sync
 #endif
 
-       /* setup the bats */
-       bl      setup_bats
-       sync
-       /* enable address translation */
-       bl      enable_addr_trans
-       sync
-
        /* enable and invalidate the data cache */
        bl      dcache_enable
        sync
@@ -1208,14 +1205,6 @@ secondary_cpu_setup:
         bl      icache_enable
         sync
         
-        /* Set up MSR and HID0, HID1*/        
-               /* Enable interrupts */
-/*        mfmsr        r28     
-        li     r4,0
-       ori     r4,r4,MSR_EE
-        or      r28,r28,r4
-        mtmsr   r28
-  */      
 
         /* TBEN  in HID0 */
        mfspr   r4, HID0