8xxx: Refactored common cpu specific code for 85xx/86xx into one file.

[oweals/u-boot.git] / cpu / mpc86xx / speed.c

diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c
index 6775a11431ab8d6ece94e7126b33f049866c8508..64a3479d7e51dc56fd52c194b98c91b7833ed1f9 100644 (file)
--- a/cpu/mpc86xx/speed.c
+++ b/cpu/mpc86xx/speed.c
@@ -28,82 +28,24 @@
 #include <common.h>
 #include <mpc86xx.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
-/*
- * get_board_sys_clk
- *     Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
- */
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
-       u8 i, go_bit, rd_clks;
-       ulong val = 0;
-
-       go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
-       go_bit &= 0x01;
-
-       rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
-       rd_clks &= 0x1C;
-
-       /*
-        * Only if both go bit and the SCLK bit in VCFGEN0 are set
-        * should we be using the AUX register. Remember, we also set the
-        * GO bit to boot from the alternate bank on the on-board flash
-        */
-
-       if (go_bit) {
-               if (rd_clks == 0x1c)
-                       i = in8(PIXIS_BASE + PIXIS_AUX);
-               else
-                       i = in8(PIXIS_BASE + PIXIS_SPD);
-       } else {
-               i = in8(PIXIS_BASE + PIXIS_SPD);
-       }
-
-       i &= 0x07;
-
-       switch (i) {
-       case 0:
-               val = 33000000;
-               break;
-       case 1:
-               val = 40000000;
-               break;
-       case 2:
-               val = 50000000;
-               break;
-       case 3:
-               val = 66000000;
-               break;
-       case 4:
-               val = 83000000;
-               break;
-       case 5:
-               val = 100000000;
-               break;
-       case 6:
-               val = 134000000;
-               break;
-       case 7:
-               val = 166000000;
-               break;
-       }
-
-       return val;
-}
+/* used in some defintiions of CONFIG_SYS_CLK_FREQ */
+extern unsigned long get_board_sys_clk(unsigned long dummy);
 
-
-void get_sys_info (sys_info_t *sysInfo)
+void get_sys_info(sys_info_t *sysInfo)
 {
-       volatile immap_t    *immap = (immap_t *)CFG_IMMR;
+       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
        volatile ccsr_gur_t *gur = &immap->im_gur;
        uint plat_ratio, e600_ratio;
+       uint lcrr_div;
 
        plat_ratio = (gur->porpllsr) & 0x0000003e;
        plat_ratio >>= 1;
 
-       switch(plat_ratio) {
+       switch (plat_ratio) {
        case 0x0:
                sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ;
                break;
@@ -120,7 +62,7 @@ void get_sys_info (sys_info_t *sysInfo)
                sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
                break;
        default:
-               sysInfo->freqSystemBus = 0;
+               sysInfo->freqSystemBus = 0;
                break;
        }
 
@@ -132,24 +74,40 @@ void get_sys_info (sys_info_t *sysInfo)
                sysInfo->freqProcessor = 2 * sysInfo->freqSystemBus;
                break;
        case 0x19:
-               sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus/2;
+               sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus / 2;
                break;
        case 0x20:
                sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus;
                break;
        case 0x39:
-               sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus/2;
+               sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus / 2;
                break;
        case 0x28:
                sysInfo->freqProcessor = 4 * sysInfo->freqSystemBus;
                break;
        case 0x1d:
-               sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus/2;
+               sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus / 2;
                break;
        default:
                sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus;
                break;
        }
+
+#if defined(CONFIG_SYS_LBC_LCRR)
+       /* We will program LCRR to this value later */
+       lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
+#else
+       {
+               volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+               lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
+       }
+#endif
+       if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
+               sysInfo->freqLocalBus = sysInfo->freqSystemBus / (lcrr_div * 2);
+       } else {
+               /* In case anyone cares what the unknown value is */
+               sysInfo->freqLocalBus = lcrr_div;
+       }
 }
 
 
@@ -160,12 +118,26 @@ void get_sys_info (sys_info_t *sysInfo)
 
 int get_clocks(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        sys_info_t sys_info;
 
        get_sys_info(&sys_info);
        gd->cpu_clk = sys_info.freqProcessor;
        gd->bus_clk = sys_info.freqSystemBus;
+       gd->lbc_clk = sys_info.freqLocalBus;
+
+       /*
+        * The base clock for I2C depends on the actual SOC.  Unfortunately,
+        * there is no pattern that can be used to determine the frequency, so
+        * the only choice is to look up the actual SOC number and use the value
+        * for that SOC. This information is taken from application note
+        * AN2919.
+        */
+#ifdef CONFIG_MPC8610
+       gd->i2c1_clk = sys_info.freqSystemBus;
+#else
+       gd->i2c1_clk = sys_info.freqSystemBus / 2;
+#endif
+       gd->i2c2_clk = gd->i2c1_clk;
 
        if (gd->cpu_clk != 0)
                return 0;