Merge commit 'u-boot/master' into for-1.3.1

[oweals/u-boot.git] / cpu / mpc86xx / spd_sdram.c

diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c
index ac9ff81ce602e1f9573254cfbcf5e26ef7ec3367..265e033fb3dca0c3d30ecfac1bbd6b55c566c20e 100644 (file)
--- a/cpu/mpc86xx/spd_sdram.c
+++ b/cpu/mpc86xx/spd_sdram.c
@@ -51,20 +51,32 @@ extern int dma_xfer(void *dest, uint count, void *src);
 #define CFG_SUPER_BANK_INTERLEAVING    0
 
 /*
- * Convert picoseconds into clock cycles (rounding up if needed).
+ * Convert picoseconds into DRAM clock cycles (rounding up if needed).
  */
 
-int
-picos_to_clk(int picos)
+static unsigned int
+picos_to_clk(unsigned int picos)
 {
-       int clks;
-
-       clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
-       if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
+       /* use unsigned long long to avoid rounding errors */
+       const unsigned long long ULL_2e12 = 2000000000000ULL;
+       unsigned long long clks;
+       unsigned long long clks_temp;
+
+       if (! picos)
+           return 0;
+
+       clks = get_bus_freq(0) * (unsigned long long) picos;
+       clks_temp = clks;
+       clks = clks / ULL_2e12;
+       if (clks_temp % ULL_2e12) {
                clks++;
        }
 
-       return clks;
+       if (clks > 0xFFFFFFFFULL) {
+               clks = 0xFFFFFFFFULL;
+       }
+
+       return (unsigned int) clks;
 }
 
 
@@ -936,19 +948,25 @@ unsigned int enable_ddr(unsigned int ddr_num)
         * Read both dimm slots and decide whether
         * or not to enable this controller.
         */
-       memset((void *)&spd1,0,sizeof(spd1));
-       memset((void *)&spd2,0,sizeof(spd2));
+       memset((void *)&spd1, 0, sizeof(spd1));
+       memset((void *)&spd2, 0, sizeof(spd2));
 
        if (ddr_num == 1) {
                CFG_READ_SPD(SPD_EEPROM_ADDRESS1,
                             0, 1, (uchar *) &spd1, sizeof(spd1));
+#if defined(SPD_EEPROM_ADDRESS2)
                CFG_READ_SPD(SPD_EEPROM_ADDRESS2,
                             0, 1, (uchar *) &spd2, sizeof(spd2));
+#endif
        } else {
+#if defined(SPD_EEPROM_ADDRESS3)
                CFG_READ_SPD(SPD_EEPROM_ADDRESS3,
                             0, 1, (uchar *) &spd1, sizeof(spd1));
+#endif
+#if defined(SPD_EEPROM_ADDRESS4)
                CFG_READ_SPD(SPD_EEPROM_ADDRESS4,
                             0, 1, (uchar *) &spd2, sizeof(spd2));
+#endif
        }
 
        /*
@@ -1093,21 +1111,27 @@ spd_sdram(void)
 {
        int memsize_ddr1_dimm1 = 0;
        int memsize_ddr1_dimm2 = 0;
+       int memsize_ddr1 = 0;
+       unsigned int law_size_ddr1;
+       volatile immap_t *immap = (immap_t *)CFG_IMMR;
+       volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+#ifdef CONFIG_DDR_INTERLEAVE
+       volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
+#endif
+
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
        int memsize_ddr2_dimm1 = 0;
        int memsize_ddr2_dimm2 = 0;
-       int memsize_total = 0;
-       int memsize_ddr1 = 0;
        int memsize_ddr2 = 0;
+       unsigned int law_size_ddr2;
+#endif
+
        unsigned int ddr1_enabled = 0;
        unsigned int ddr2_enabled = 0;
-       unsigned int law_size_ddr1;
-       unsigned int law_size_ddr2;
-       volatile immap_t *immap = (immap_t *)CFG_IMMR;
-       volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+       int memsize_total = 0;
 
 #ifdef CONFIG_DDR_INTERLEAVE
        unsigned int law_size_interleaved;
-       volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
        volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2;
 
        memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
@@ -1182,9 +1206,11 @@ spd_sdram(void)
                                      (unsigned int)memsize_total * 1024*1024);
        memsize_total += memsize_ddr1_dimm1;
 
+#if defined(SPD_EEPROM_ADDRESS2)
        memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2,
                                      1, 2,
                                      (unsigned int)memsize_total * 1024*1024);
+#endif
        memsize_total += memsize_ddr1_dimm2;
 
        /*
@@ -1246,10 +1272,12 @@ spd_sdram(void)
                debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
                debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
        }
+
+       debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2);
+
 #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
 
-       debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n",
-             memsize_ddr1, memsize_ddr2);
+       debug("\nMemory size of DDR1 = 0x%08lx\n", memsize_ddr1);
 
        /*
         * If neither DDR controller is enabled return 0.