Merge git://www.denx.de/git/u-boot

[oweals/u-boot.git] / cpu / mpc86xx / cpu_init.c

diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index 582ac6ba95fd6efdda2bbfdb034d468cd30b3e30..4673d05e7193031f22ac54ef47f5826de8ecdc15 100644 (file)
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -1,6 +1,6 @@
 /*
  * Copyright 2004 Freescale Semiconductor.
- * Jeff Brown (jeffrey@freescale.com)
+ * Jeff Brown
  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -36,14 +36,13 @@
  * initialize a bunch of registers
  */
 
-void cpu_init_f (void)
+void cpu_init_f(void)
 {
-        DECLARE_GLOBAL_DATA_PTR;
+       DECLARE_GLOBAL_DATA_PTR;
        volatile immap_t    *immap = (immap_t *)CFG_IMMR;
        volatile ccsr_lbc_t *memctl = &immap->im_lbc;
-        //u8 val;
-        
-        /* Pointer is writable since we allocated a register for it */
+
+       /* Pointer is writable since we allocated a register for it */
        gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
 
        /* Clear initial global data */
@@ -72,23 +71,21 @@ void cpu_init_f (void)
        memctl->br1 = CFG_BR1_PRELIM;
 #endif
 
-        //#if !defined(CONFIG_MPC86xx)
 #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
        memctl->or2 = CFG_OR2_PRELIM;
        memctl->br2 = CFG_BR2_PRELIM;
 #endif
-        //#endif
-       
+
 #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
        memctl->or3 = CFG_OR3_PRELIM;
        memctl->br3 = CFG_BR3_PRELIM;
 #endif
-       
+
 #if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
        memctl->or4 = CFG_OR4_PRELIM;
        memctl->br4 = CFG_BR4_PRELIM;
 #endif
-       
+
 #if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
        memctl->or5 = CFG_OR5_PRELIM;
        memctl->br5 = CFG_BR5_PRELIM;
@@ -107,28 +104,14 @@ void cpu_init_f (void)
        /* enable the timebase bit in HID0 */
        set_hid0(get_hid0() | 0x4000000);
 
-        /* enable SYNCBE | ABE bits in  HID1 */
-        set_hid1(get_hid1() | 0x00000C00);
-
-        /* Since the bats have been set up at this point and
-         * the local bus registers have been initialized, we
-         * turn on the WDEN bit in PIXIS_VCTL
-         */
-/*         val = in8(PIXIS_BASE+PIXIS_VCTL); */
-        /* Set the WDEN */
-/*         val |= 0x08; */
-/*         out8(PIXIS_BASE+PIXIS_VCTL,val);  */
+       /* enable SYNCBE | ABE bits in  HID1 */
+       set_hid1(get_hid1() | 0x00000C00);
 }
 
 /*
  * initialize higher level parts of CPU like timers
  */
-int cpu_init_r (void)
+int cpu_init_r(void)
 {
-       return (0);
+       return 0;
 }
-
-
-
-
-