POWERPC 86xx: Move BAT setup code to C

[oweals/u-boot.git] / cpu / mpc86xx / cpu_init.c

diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index c816c18974ca6673cb8994aafefdeff50f617a2a..1fda3fe805226ffce838f355bff9c4e2148df024 100644 (file)
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -1,6 +1,6 @@
 /*
  * Copyright 2004 Freescale Semiconductor.
- * Jeff Brown (jeffrey@freescale.com)
+ * Jeff Brown
  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -26,8 +26,13 @@
  * cpu_init.c - low level cpu init
  */
 
+#include <config.h>
 #include <common.h>
 #include <mpc86xx.h>
+#include <asm/mmu.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /*
  * Breathe some life into the CPU...
@@ -38,16 +43,19 @@
 
 void cpu_init_f(void)
 {
-        DECLARE_GLOBAL_DATA_PTR;
        volatile immap_t    *immap = (immap_t *)CFG_IMMR;
        volatile ccsr_lbc_t *memctl = &immap->im_lbc;
 
-        /* Pointer is writable since we allocated a register for it */
+       /* Pointer is writable since we allocated a register for it */
        gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
 
        /* Clear initial global data */
        memset ((void *) gd, 0, sizeof (gd_t));
 
+#ifdef CONFIG_FSL_LAW
+       init_laws();
+#endif
+
        /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
         * addresses - these have to be modified later when FLASH size
         * has been determined
@@ -104,17 +112,8 @@ void cpu_init_f(void)
        /* enable the timebase bit in HID0 */
        set_hid0(get_hid0() | 0x4000000);
 
-        /* enable SYNCBE | ABE bits in  HID1 */
-        set_hid1(get_hid1() | 0x00000C00);
-
-        /* Since the bats have been set up at this point and
-         * the local bus registers have been initialized, we
-         * turn on the WDEN bit in PIXIS_VCTL
-         */
-/*         val = in8(PIXIS_BASE+PIXIS_VCTL); */
-        /* Set the WDEN */
-/*         val |= 0x08; */
-/*         out8(PIXIS_BASE+PIXIS_VCTL,val);  */
+       /* enable EMCP, SYNCBE | ABE bits in HID1 */
+       set_hid1(get_hid1() | 0x80000C00);
 }
 
 /*
@@ -125,7 +124,25 @@ int cpu_init_r(void)
        return 0;
 }
 
-
-
-
-
+/* Set up BAT registers */
+void setup_bats(void)
+{
+       write_bat(DBAT0, CFG_DBAT0U, CFG_DBAT0L);
+       write_bat(IBAT0, CFG_IBAT0U, CFG_IBAT0L);
+       write_bat(DBAT1, CFG_DBAT1U, CFG_DBAT1L);
+       write_bat(IBAT1, CFG_IBAT1U, CFG_IBAT1L);
+       write_bat(DBAT2, CFG_DBAT2U, CFG_DBAT2L);
+       write_bat(IBAT2, CFG_IBAT2U, CFG_IBAT2L);
+       write_bat(DBAT3, CFG_DBAT3U, CFG_DBAT3L);
+       write_bat(IBAT3, CFG_IBAT3U, CFG_IBAT3L);
+       write_bat(DBAT4, CFG_DBAT4U, CFG_DBAT4L);
+       write_bat(IBAT4, CFG_IBAT4U, CFG_IBAT4L);
+       write_bat(DBAT5, CFG_DBAT5U, CFG_DBAT5L);
+       write_bat(IBAT5, CFG_IBAT5U, CFG_IBAT5L);
+       write_bat(DBAT6, CFG_DBAT6U, CFG_DBAT6L);
+       write_bat(IBAT6, CFG_IBAT6U, CFG_IBAT6L);
+       write_bat(DBAT7, CFG_DBAT7U, CFG_DBAT7L);
+       write_bat(IBAT7, CFG_IBAT7U, CFG_IBAT7L);
+
+       return;
+}