#include <asm/cache.h>
#include <asm/mmu.h>
#include <mpc86xx.h>
+#include <tsec.h>
#include <asm/fsl_law.h>
uint pvr, svr;
uint ver;
uint major, minor;
- uint lcrr; /* local bus clock ratio register */
- uint clkdiv; /* clock divider portion of lcrr */
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
puts("Freescale PowerPC\n");
printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
-#if defined(CFG_LBC_LCRR)
- lcrr = CFG_LBC_LCRR;
-#else
- {
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
-
- lcrr = lbc->lcrr;
- }
-#endif
- clkdiv = lcrr & 0x0f;
- if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
- printf("LBC:%4lu MHz\n",
- sysinfo.freqSystemBus / 1000000 / clkdiv);
+ if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
+ printf("LBC:%4lu MHz\n", sysinfo.freqLocalBus / 1000000);
} else {
- printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
+ printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
+ sysinfo.freqLocalBus);
}
puts(" L2: ");
{
#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
-#ifdef CFG_RESET_ADDRESS
- ulong addr = CFG_RESET_ADDRESS;
+#ifdef CONFIG_SYS_RESET_ADDRESS
+ ulong addr = CONFIG_SYS_RESET_ADDRESS;
#else
/*
- * note: when CFG_MONITOR_BASE points to a RAM address,
- * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
+ * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
+ * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid
* address. Better pick an address known to be invalid on your
- * system and assign it to CFG_RESET_ADDRESS.
+ * system and assign it to CONFIG_SYS_RESET_ADDRESS.
*/
- ulong addr = CFG_MONITOR_BASE - sizeof(ulong);
+ ulong addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
#endif
/* flush and disable I/D cache */
/*
* This actually feed the hard enabled watchdog.
*/
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_wdt_t *wdt = &immap->im_wdt;
volatile ccsr_gur_t *gur = &immap->im_gur;
u32 tmp = gur->pordevsr;
void
dma_init(void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
dma->satr0 = 0x00040000;
uint
dma_check(void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
volatile uint status = dma->sr0;
int
dma_xfer(void *dest, uint count, void *src)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_dma_t *dma = &immap->im_dma;
dma->dar0 = (uint) dest;
*/
void mpc86xx_reginfo(void)
{
- immap_t *immap = (immap_t *)CFG_IMMR;
+ immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
ccsr_lbc_t *lbc = &immap->im_lbc;
print_bats();
printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
}
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_TSEC_ENET)
+ tsec_standard_init(bis);
+#endif
+
+ return 0;
+}