Merge branch 'fixes' into cleanups

[oweals/u-boot.git] / cpu / mpc85xx / start.S

diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 25d039056e8e7b2cc99e8b5843bcba2c767435ce..8fa0ff7a8a591148e81069ce67ccb748ec38c1a2 100644 (file)
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -30,6 +30,7 @@
 
 #include <config.h>
 #include <mpc85xx.h>
+#include <timestamp.h>
 #include <version.h>
 
 #define _LINUX_CONFIG_H 1      /* avoid reading Linux autoconf.h file  */
@@ -163,8 +164,10 @@ _start_e500:
        ori     r0,r0,HID0_TBEN@l       /* Enable Timebase */
        mtspr   HID0,r0
 
+#ifndef CONFIG_E500MC
        li      r0,(HID1_ASTME|HID1_ABE)@l      /* Addr streaming & broadcast */
        mtspr   HID1,r0
+#endif
 
        /* Enable Branch Prediction */
 #if defined(CONFIG_BTB)
@@ -272,7 +275,7 @@ _start:
        .globl  version_string
 version_string:
        .ascii U_BOOT_VERSION
-       .ascii " (", __DATE__, " - ", __TIME__, ")"
+       .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
        .ascii CONFIG_IDENT_STRING, "\0"
 
        .align  4
@@ -565,6 +568,7 @@ mck_return:
 
 /* Cache functions.
 */
+.globl invalidate_icache
 invalidate_icache:
        mfspr   r0,L1CSR1
        ori     r0,r0,L1CSR1_ICFI
@@ -574,6 +578,7 @@ invalidate_icache:
        isync
        blr                             /* entire I cache */
 
+.globl invalidate_dcache
 invalidate_dcache:
        mfspr   r0,L1CSR0
        ori     r0,r0,L1CSR0_DCFI
@@ -996,8 +1001,8 @@ trap_reloc:
 .globl unlock_ram_in_cache
 unlock_ram_in_cache:
        /* invalidate the INIT_RAM section */
-       lis     r3,(CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
-       ori     r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
+       lis     r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
+       ori     r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
        mfspr   r4,L1CFG0
        andi.   r4,r4,0x1ff
        slwi    r4,r4,(10 - 1 - L1_CACHE_SHIFT)
@@ -1019,3 +1024,50 @@ unlock_ram_in_cache:
        tlbivax 0,r3
        isync
        blr
+
+.globl flush_dcache
+flush_dcache:
+       mfspr   r3,SPRN_L1CFG0
+
+       rlwinm  r5,r3,9,3       /* Extract cache block size */
+       twlgti  r5,1            /* Only 32 and 64 byte cache blocks
+                                * are currently defined.
+                                */
+       li      r4,32
+       subfic  r6,r5,2         /* r6 = log2(1KiB / cache block size) -
+                                *      log2(number of ways)
+                                */
+       slw     r5,r4,r5        /* r5 = cache block size */
+
+       rlwinm  r7,r3,0,0xff    /* Extract number of KiB in the cache */
+       mulli   r7,r7,13        /* An 8-way cache will require 13
+                                * loads per set.
+                                */
+       slw     r7,r7,r6
+
+       /* save off HID0 and set DCFA */
+       mfspr   r8,SPRN_HID0
+       ori     r9,r8,HID0_DCFA@l
+       mtspr   SPRN_HID0,r9
+       isync
+
+       lis     r4,0
+       mtctr   r7
+
+1:     lwz     r3,0(r4)        /* Load... */
+       add     r4,r4,r5
+       bdnz    1b
+
+       msync
+       lis     r4,0
+       mtctr   r7
+
+1:     dcbf    0,r4            /* ...and flush. */
+       add     r4,r4,r5
+       bdnz    1b
+
+       /* restore HID0 */
+       mtspr   SPRN_HID0,r8
+       isync
+
+       blr