Merge commit 'wd/master'

[oweals/u-boot.git] / cpu / mpc85xx / start.S

diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index eb24dbc430715294feea0aeac3aa49a864f0ca2c..2b5d90e27848d0cde207f5f359f3bc312e97d3c5 100644 (file)
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -89,7 +89,7 @@ _start_e500:
        /* L1 */
        li      r0,2
        mtspr   L1CSR0,r0       /* invalidate d-cache */
-       mtspr   L1CSR1,r0       /* invalidate i-cache */
+       mtspr   L1CSR1,r0       /* invalidate i-cache */
 
        mfspr   r1,DBSR
        mtspr   DBSR,r1         /* Clear all valid bits */
@@ -992,7 +992,6 @@ trap_reloc:
 
        blr
 
-#ifdef CFG_INIT_RAM_LOCK
 .globl unlock_ram_in_cache
 unlock_ram_in_cache:
        /* invalidate the INIT_RAM section */
@@ -1002,11 +1001,20 @@ unlock_ram_in_cache:
        andi.   r4,r4,0x1ff
        slwi    r4,r4,(10 - 1 - L1_CACHE_SHIFT)
        mtctr   r4
-1:     icbi    r0,r3
-       dcbi    r0,r3
+1:     dcbi    r0,r3
        addi    r3,r3,CFG_CACHELINE_SIZE
        bdnz    1b
-       sync                    /* Wait for all icbi to complete on bus */
+       sync
+
+       /* Invalidate the TLB entries for the cache */
+       lis     r3,CFG_INIT_RAM_ADDR@h
+       ori     r3,r3,CFG_INIT_RAM_ADDR@l
+       tlbivax 0,r3
+       addi    r3,r3,0x1000
+       tlbivax 0,r3
+       addi    r3,r3,0x1000
+       tlbivax 0,r3
+       addi    r3,r3,0x1000
+       tlbivax 0,r3
        isync
        blr
-#endif