/* L1 */
li r0,2
mtspr L1CSR0,r0 /* invalidate d-cache */
- mtspr L1CSR1,r0 /* invalidate i-cache */
+ mtspr L1CSR1,r0 /* invalidate i-cache */
mfspr r1,DBSR
mtspr DBSR,r1 /* Clear all valid bits */
blr
-#ifdef CFG_INIT_RAM_LOCK
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
andi. r4,r4,0x1ff
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr r4
-1: icbi r0,r3
- dcbi r0,r3
+1: dcbi r0,r3
addi r3,r3,CFG_CACHELINE_SIZE
bdnz 1b
- sync /* Wait for all icbi to complete on bus */
+ sync
/* Invalidate the TLB entries for the cache */
lis r3,CFG_INIT_RAM_ADDR@h
tlbivax 0,r3
isync
blr
-#endif