Merge git://git.denx.de/u-boot into u-boot

[oweals/u-boot.git] / cpu / mpc85xx / speed.c

diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index d9f9a8c38a7201d66c328923e2dad0533f94e40f..b0f47e042e96455120d38e397f8f20c6d0397648 100644 (file)
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -28,6 +28,7 @@
 #include <common.h>
 #include <ppc_asm.tmpl>
 #include <asm/processor.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -37,17 +38,20 @@ void get_sys_info (sys_info_t * sysInfo)
 {
        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
        uint plat_ratio,e500_ratio,half_freqSystemBus;
+       uint lcrr_div;
+       int i;
 
        plat_ratio = (gur->porpllsr) & 0x0000003e;
        plat_ratio >>= 1;
        sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
-       e500_ratio = (gur->porpllsr) & 0x003f0000;
-       e500_ratio >>= 16;
 
        /* Divide before multiply to avoid integer
         * overflow for processor speeds above 2GHz */
        half_freqSystemBus = sysInfo->freqSystemBus/2;
-       sysInfo->freqProcessor = e500_ratio*half_freqSystemBus;
+       for (i = 0; i < CONFIG_NUM_CPUS; i++) {
+               e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
+               sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
+       }
 
        /* Note: freqDDRBus is the MCLK frequency, not the data rate. */
        sysInfo->freqDDRBus = sysInfo->freqSystemBus;
@@ -60,6 +64,30 @@ void get_sys_info (sys_info_t * sysInfo)
                        sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
        }
 #endif
+
+#if defined(CONFIG_SYS_LBC_LCRR)
+       /* We will program LCRR to this value later */
+       lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
+#else
+       {
+           volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+           lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
+       }
+#endif
+       if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
+#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
+    !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
+               /*
+                * Yes, the entire PQ38 family use the same
+                * bit-representation for twice the clock divider values.
+                */
+               lcrr_div *= 2;
+#endif
+               sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
+       } else {
+               /* In case anyone cares what the unknown value is */
+               sysInfo->freqLocalBus = lcrr_div;
+       }
 }
 
 
@@ -79,9 +107,10 @@ int get_clocks (void)
        dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
 #endif
        get_sys_info (&sys_info);
-       gd->cpu_clk = sys_info.freqProcessor;
+       gd->cpu_clk = sys_info.freqProcessor[0];
        gd->bus_clk = sys_info.freqSystemBus;
        gd->mem_clk = sys_info.freqDDRBus;
+       gd->lbc_clk = sys_info.freqLocalBus;
 
        /*
         * The base clock for I2C depends on the actual SOC.  Unfortunately,
@@ -102,9 +131,9 @@ int get_clocks (void)
         * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
         */
        if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
-               gd->i2c1_clk = sys_info.freqSystemBus / 2;
-       else
                gd->i2c1_clk = sys_info.freqSystemBus / 3;
+       else
+               gd->i2c1_clk = sys_info.freqSystemBus / 2;
 #else
        /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
        gd->i2c1_clk = sys_info.freqSystemBus / 2;