Merge commit 'wd/master'

[oweals/u-boot.git] / cpu / mpc85xx / speed.c

diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 952f30cf3994e8c7d2c5890a6a12c6561dbcbc3f..699441b46a48c97b87247b5d28201d1ff6b5e9e8 100644 (file)
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -48,6 +48,8 @@ void get_sys_info (sys_info_t * sysInfo)
         * overflow for processor speeds above 2GHz */
        half_freqSystemBus = sysInfo->freqSystemBus/2;
        sysInfo->freqProcessor = e500_ratio*half_freqSystemBus;
+
+       /* Note: freqDDRBus is the MCLK frequency, not the data rate. */
        sysInfo->freqDDRBus = sysInfo->freqSystemBus;
 
 #ifdef CONFIG_DDR_CLK_FREQ
@@ -63,6 +65,9 @@ void get_sys_info (sys_info_t * sysInfo)
 int get_clocks (void)
 {
        sys_info_t sys_info;
+#ifdef CONFIG_MPC8544
+       volatile ccsr_gur_t *gur = (void *) CFG_MPC85xx_GUTS_ADDR;
+#endif
 #if defined(CONFIG_CPM2)
        volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
        uint sccr, dfbrg;
@@ -75,8 +80,35 @@ int get_clocks (void)
        get_sys_info (&sys_info);
        gd->cpu_clk = sys_info.freqProcessor;
        gd->bus_clk = sys_info.freqSystemBus;
+       gd->mem_clk = sys_info.freqDDRBus;
+
+       /*
+        * The base clock for I2C depends on the actual SOC.  Unfortunately,
+        * there is no pattern that can be used to determine the frequency, so
+        * the only choice is to look up the actual SOC number and use the value
+        * for that SOC. This information is taken from application note
+        * AN2919.
+        */
+#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
+       defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
        gd->i2c1_clk = sys_info.freqSystemBus;
-       gd->i2c2_clk = sys_info.freqSystemBus;
+#elif defined(CONFIG_MPC8544)
+       /*
+        * On the 8544, the I2C clock is the same as the SEC clock.  This can be
+        * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
+        * 4.4.3.3 of the 8544 RM.  Note that this might actually work for all
+        * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
+        * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
+        */
+       if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
+               gd->i2c1_clk = sys_info.freqSystemBus / 3;
+       else
+               gd->i2c1_clk = sys_info.freqSystemBus / 2;
+#else
+       /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
+       gd->i2c1_clk = sys_info.freqSystemBus / 2;
+#endif
+       gd->i2c2_clk = gd->i2c1_clk;
 
 #if defined(CONFIG_CPM2)
        gd->vco_out = 2*sys_info.freqSystemBus;
@@ -96,14 +128,7 @@ int get_clocks (void)
  *********************************************/
 ulong get_bus_freq (ulong dummy)
 {
-       ulong val;
-
-       sys_info_t sys_info;
-
-       get_sys_info (&sys_info);
-       val = sys_info.freqSystemBus;
-
-       return val;
+       return gd->bus_clk;
 }
 
 /********************************************
@@ -112,12 +137,5 @@ ulong get_bus_freq (ulong dummy)
  *********************************************/
 ulong get_ddr_freq (ulong dummy)
 {
-       ulong val;
-
-       sys_info_t sys_info;
-
-       get_sys_info (&sys_info);
-       val = sys_info.freqDDRBus;
-
-       return val;
+       return gd->mem_clk;
 }