Merge branch 'master' of git://www.denx.de/git/u-boot-video
[oweals/u-boot.git] / cpu / mpc85xx / spd_sdram.c
index 90c3d444a8753a164fb90e6f47d7dc7d63974617..435458a18930b482394c79b458a397ef974c3dcd 100644 (file)
@@ -306,7 +306,7 @@ spd_sdram(void)
         * Adjust DDR II IO voltage biasing.
         * Only 8548 rev 1 needs the fix
         */
-       if ((SVR_VER(get_svr()) == SVR_8548_E) &&
+       if ((SVR_SOC_VER(get_svr()) == SVR_8548_E) &&
                        (SVR_MJREV(get_svr()) == 1) &&
                        (spd.mem_type == SPD_MEMTYPE_DDR2)) {
                volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
@@ -1071,19 +1071,9 @@ setup_laws_and_tlbs(unsigned int memsize)
        ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
        while (ram_tlb_address < (memsize * 1024 * 1024)
              && ram_tlb_index < 16) {
-               mtspr(MAS0, FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
-               mtspr(MAS1, FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
-               mtspr(MAS2, FSL_BOOKE_MAS2(ram_tlb_address, 0));
-               mtspr(MAS3, FSL_BOOKE_MAS3(ram_tlb_address, 0,
-                       (MAS3_SX|MAS3_SW|MAS3_SR)));
-               asm volatile("isync;msync;tlbwe;isync");
-
-               debug("DDR: MAS0=0x%08x\n", FSL_BOOKE_MAS0(1, ram_tlb_index, 0));
-               debug("DDR: MAS1=0x%08x\n", FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size));
-               debug("DDR: MAS2=0x%08x\n", FSL_BOOKE_MAS2(ram_tlb_address, 0));
-               debug("DDR: MAS3=0x%08x\n",
-                       FSL_BOOKE_MAS3(ram_tlb_address, 0,
-                                     (MAS3_SX|MAS3_SW|MAS3_SR)));
+               set_tlb(1, ram_tlb_address, ram_tlb_address,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, ram_tlb_index, tlb_size, 1);
 
                ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
                ram_tlb_index++;