OMAP3: Fix timer handling to 1ms and CONFIG_SYS_HZ to 1000

[oweals/u-boot.git] / cpu / mpc85xx / release.S

diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index ec5e4daf88f1b09838f4a425f4742fe7acb1024e..fbefc2c31e1784bde7dfe9cdf5856b8447604ddb 100644 (file)
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -24,14 +24,18 @@
 __secondary_start_page:
 /* First do some preliminary setup */
        lis     r3, HID0_EMCP@h         /* enable machine check */
+#ifndef CONFIG_E500MC
        ori     r3,r3,HID0_TBEN@l       /* enable Timebase */
+#endif
 #ifdef CONFIG_PHYS_64BIT
        ori     r3,r3,HID0_ENMAS7@l     /* enable MAS7 updates */
 #endif
        mtspr   SPRN_HID0,r3
 
+#ifndef CONFIG_E500MC
        li      r3,(HID1_ASTME|HID1_ABE)@l      /* Addr streaming & broadcast */
        mtspr   SPRN_HID1,r3
+#endif
 
        /* Enable branch prediction */
        li      r3,0x201
@@ -64,10 +68,30 @@ __secondary_start_page:
 
        /* r10 has the base address for the entry */
        mfspr   r0,SPRN_PIR
+#ifdef CONFIG_E500MC
+       rlwinm  r4,r0,27,27,31
+#else
        mr      r4,r0
+#endif
        slwi    r8,r4,5
        add     r10,r3,r8
 
+#ifdef CONFIG_BACKSIDE_L2_CACHE
+       /* Enable/invalidate the L2 cache */
+       msync
+       lis     r3,L2CSR0_L2FI@h
+       mtspr   SPRN_L2CSR0,r3
+1:
+       mfspr   r3,SPRN_L2CSR0
+       andis.  r1,r3,L2CSR0_L2FI@h
+       bne     1b
+
+       lis     r3,CONFIG_SYS_INIT_L2CSR0@h
+       ori     r3,r3,CONFIG_SYS_INIT_L2CSR0@l
+       mtspr   SPRN_L2CSR0,r3
+       isync
+#endif
+
 #define EPAPR_MAGIC            (0x45504150)
 #define ENTRY_ADDR_UPPER       0
 #define ENTRY_ADDR_LOWER       4
@@ -149,6 +173,7 @@ __secondary_start_page:
        mfspr   r0,SPRN_PIR
        stw     r0,ENTRY_PIR(r10)
 
+       mtspr   IVPR,r12
 /*
  * Coming here, we know the cpu has one TLB mapping in TLB1[0]
  * which maps 0xfffff000-0xffffffff one-to-one.  We set up a