Merge branch 'master' of git://www.denx.de/git/u-boot-mips

[oweals/u-boot.git] / cpu / mpc85xx / interrupts.c

diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c
index dc246dca02878bff9ce8290295616176b4abb9c2..18e5377b32ba7c7abdd31f5e8c83ccfe38029750 100644 (file)
--- a/cpu/mpc85xx/interrupts.c
+++ b/cpu/mpc85xx/interrupts.c
@@ -80,15 +80,46 @@ int disable_interrupts (void)
 
 int interrupt_init (void)
 {
-       volatile immap_t *immr = (immap_t *)CFG_IMMR;
+       volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
 
-       immr->im_pic.gcr = MPC85xx_PICGCR_RST;
-       while (immr->im_pic.gcr & MPC85xx_PICGCR_RST);
-       immr->im_pic.gcr = MPC85xx_PICGCR_M;
+       pic->gcr = MPC85xx_PICGCR_RST;
+       while (pic->gcr & MPC85xx_PICGCR_RST);
+       pic->gcr = MPC85xx_PICGCR_M;
        decrementer_count = get_tbclk() / CFG_HZ;
        mtspr(SPRN_TCR, TCR_PIE);
        set_dec (decrementer_count);
        set_msr (get_msr () | MSR_EE);
+
+#ifdef CONFIG_INTERRUPTS
+       pic->iivpr1 = 0x810002; /* 50220 enable ecm interrupts */
+       debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1);
+
+       pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
+       debug("iivpr2@%x = %x\n",&pic->iivpr2, pic->iivpr2);
+
+       pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
+       debug("iivpr3@%x = %x\n",&pic->iivpr3, pic->iivpr3);
+
+#ifdef CONFIG_PCI1
+       pic->iivpr8 = 0x810008; /* enable pci1 interrupts */
+       debug("iivpr8@%x = %x\n",&pic->iivpr8, pic->iivpr8);
+#endif
+#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
+       pic->iivpr9 = 0x810009; /* enable pci1 interrupts */
+       debug("iivpr9@%x = %x\n",&pic->iivpr9, pic->iivpr9);
+#endif
+#ifdef CONFIG_PCIE1
+       pic->iivpr10 = 0x81000a;        /* enable pcie1 interrupts */
+       debug("iivpr10@%x = %x\n",&pic->iivpr10, pic->iivpr10);
+#endif
+#ifdef CONFIG_PCIE3
+       pic->iivpr11 = 0x81000b;        /* enable pcie3 interrupts */
+       debug("iivpr11@%x = %x\n",&pic->iivpr11, pic->iivpr11);
+#endif
+
+       pic->ctpr=0;            /* 40080 clear current task priority register */
+#endif
+
        return (0);
 }