OMAP3: Fix timer handling to 1ms and CONFIG_SYS_HZ to 1000

[oweals/u-boot.git] / cpu / mpc85xx / ddr-gen3.c

diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c
index a2b45c5719ebde1c1345a232785d2fc965bbe251..8ac3d5fbebf4779f9c672c536bbe89cc2ccd00da 100644 (file)
--- a/cpu/mpc85xx/ddr-gen3.c
+++ b/cpu/mpc85xx/ddr-gen3.c
@@ -19,6 +19,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 {
        unsigned int i;
        volatile ccsr_ddr_t *ddr;
+       u32 temp_sdram_cfg;
 
        switch (ctrl_num) {
        case 0:
@@ -78,6 +79,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
        out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 
+       /* Set, but do not enable the memory */
+       temp_sdram_cfg = regs->ddr_sdram_cfg;
+       temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
+       out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
        /*
         * For 8572 DDR1 erratum - DDR controller may enter illegal state
         * when operatiing in 32-bit bus mode with 4-beat bursts,
@@ -93,13 +98,17 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 #endif
 
        /*
-        * 200 painful micro-seconds must elapse between
+        * 500 painful micro-seconds must elapse between
         * the DDR clock setup and the DDR config enable.
+        * DDR2 need 200 us, and DDR3 need 500 us from spec,
+        * we choose the max, that is 500 us for all of case.
         */
-       udelay(200);
+       udelay(500);
        asm volatile("sync;isync");
 
-       out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
+       /* Let the controller go */
+       temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
+       out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 
        /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
        while (in_be32(&ddr->sdram_cfg_2) & 0x10) {