{
unsigned int i;
volatile ccsr_ddr_t *ddr;
+ u32 temp_sdram_cfg;
switch (ctrl_num) {
case 0:
out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
+ /* Set, but do not enable the memory */
+ temp_sdram_cfg = regs->ddr_sdram_cfg;
+ temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
+ out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
/*
* For 8572 DDR1 erratum - DDR controller may enter illegal state
* when operatiing in 32-bit bus mode with 4-beat bursts,
#endif
/*
- * 200 painful micro-seconds must elapse between
+ * 500 painful micro-seconds must elapse between
* the DDR clock setup and the DDR config enable.
+ * DDR2 need 200 us, and DDR3 need 500 us from spec,
+ * we choose the max, that is 500 us for all of case.
*/
- udelay(200);
+ udelay(500);
asm volatile("sync;isync");
- out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
+ /* Let the controller go */
+ temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
+ out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
while (in_be32(&ddr->sdram_cfg_2) & 0x10) {