OMAP3: Fix timer handling to 1ms and CONFIG_SYS_HZ to 1000

[oweals/u-boot.git] / cpu / mpc85xx / ddr-gen3.c

diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c
index 8dc2b3ac528bd66894778224c4c531c3c05903bd..8ac3d5fbebf4779f9c672c536bbe89cc2ccd00da 100644 (file)
--- a/cpu/mpc85xx/ddr-gen3.c
+++ b/cpu/mpc85xx/ddr-gen3.c
@@ -79,8 +79,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
        out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 
-       /* Do not enable the memory */
-       temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
+       /* Set, but do not enable the memory */
+       temp_sdram_cfg = regs->ddr_sdram_cfg;
        temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
        out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
        /*
@@ -98,10 +98,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 #endif
 
        /*
-        * 200 painful micro-seconds must elapse between
+        * 500 painful micro-seconds must elapse between
         * the DDR clock setup and the DDR config enable.
+        * DDR2 need 200 us, and DDR3 need 500 us from spec,
+        * we choose the max, that is 500 us for all of case.
         */
-       udelay(200);
+       udelay(500);
        asm volatile("sync;isync");
 
        /* Let the controller go */