out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
- /* Do not enable the memory */
- temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
+ /* Set, but do not enable the memory */
+ temp_sdram_cfg = regs->ddr_sdram_cfg;
temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
/*
#endif
/*
- * 200 painful micro-seconds must elapse between
+ * 500 painful micro-seconds must elapse between
* the DDR clock setup and the DDR config enable.
+ * DDR2 need 200 us, and DDR3 need 500 us from spec,
+ * we choose the max, that is 500 us for all of case.
*/
- udelay(200);
+ udelay(500);
asm volatile("sync;isync");
/* Let the controller go */