Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx

[oweals/u-boot.git] / cpu / mpc85xx / cpu_init.c

diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index c7fe130ee0eee75217f98880dd00aa54ba6afc84..fdb9ecbd509b47f84077cca8cd5ac8c07c0a5229 100644 (file)
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -34,9 +34,32 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_QE
+extern qe_iop_conf_t qe_iop_conf_tab[];
+extern void qe_config_iopin(u8 port, u8 pin, int dir,
+                               int open_drain, int assign);
+extern void qe_init(uint qe_base);
+extern void qe_reset(void);
+
+static void config_qe_ioports(void)
+{
+       u8      port, pin;
+       int     dir, open_drain, assign;
+       int     i;
+
+       for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
+               port            = qe_iop_conf_tab[i].port;
+               pin             = qe_iop_conf_tab[i].pin;
+               dir             = qe_iop_conf_tab[i].dir;
+               open_drain      = qe_iop_conf_tab[i].open_drain;
+               assign          = qe_iop_conf_tab[i].assign;
+               qe_config_iopin(port, pin, dir, open_drain, assign);
+       }
+}
+#endif
 
 #ifdef CONFIG_CPM2
-static void config_8560_ioports (volatile immap_t * immr)
+void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 {
        int portnum;
 
@@ -76,7 +99,7 @@ static void config_8560_ioports (volatile immap_t * immr)
                }
 
                if (pmsk != 0) {
-                       volatile ioport_t *iop = ioport_addr (immr, portnum);
+                       volatile ioport_t *iop = ioport_addr (cpm, portnum);
                        uint tpmsk = ~pmsk;
 
                        /*
@@ -108,8 +131,7 @@ static void config_8560_ioports (volatile immap_t * immr)
 
 void cpu_init_f (void)
 {
-       volatile immap_t    *immap = (immap_t *)CFG_IMMR;
-       volatile ccsr_lbc_t *memctl = &immap->im_lbc;
+       volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
        extern void m8560_cpm_reset (void);
 
        /* Pointer is writable since we allocated a register for it */
@@ -120,7 +142,7 @@ void cpu_init_f (void)
 
 
 #ifdef CONFIG_CPM2
-       config_8560_ioports(immap);
+       config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR);
 #endif
 
        /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
@@ -181,6 +203,11 @@ void cpu_init_f (void)
 #if defined(CONFIG_CPM2)
        m8560_cpm_reset();
 #endif
+#ifdef CONFIG_QE
+       /* Config QE ioports */
+       config_qe_ioports();
+#endif
+
 }
 
 
@@ -194,18 +221,15 @@ void cpu_init_f (void)
 
 int cpu_init_r(void)
 {
-#if defined(CONFIG_CLEAR_LAW0) || defined(CONFIG_L2_CACHE)
-       volatile immap_t    *immap = (immap_t *)CFG_IMMR;
-#endif
 #ifdef CONFIG_CLEAR_LAW0
-       volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+       volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
 
        /* clear alternate boot location LAW (used for sdram, or ddr bank) */
        ecm->lawar0 = 0;
 #endif
 
 #if defined(CONFIG_L2_CACHE)
-       volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
+       volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
        volatile uint cache_ctl;
        uint svr, ver;
        uint l2srbar;
@@ -219,7 +243,7 @@ int cpu_init_r(void)
        switch (cache_ctl & 0x30000000) {
        case 0x20000000:
                if (ver == SVR_8548 || ver == SVR_8548_E ||
-                   ver == SVR_8544) {
+                   ver == SVR_8544 || ver == SVR_8568_E) {
                        printf ("L2 cache 512KB:");
                        /* set L2E=1, L2I=1, & L2SRAM=0 */
                        cache_ctl = 0xc0000000;
@@ -262,6 +286,11 @@ int cpu_init_r(void)
 #else
        printf("L2 cache: disabled\n");
 #endif
+#ifdef CONFIG_QE
+       uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */
+       qe_init(qe_base);
+       qe_reset();
+#endif
 
        return 0;
 }