Merge branch 'socrates' of /home/wd/git/u-boot/projects

[oweals/u-boot.git] / cpu / mpc85xx / cpu_init.c

diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 9a65142e3c925c2a53a1648359392b5af5ea6429..e3240b519ee8d5d44fe716d6a74edbcf88458565 100644 (file)
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -31,7 +31,9 @@
 #include <asm/processor.h>
 #include <ioports.h>
 #include <asm/io.h>
+#include <asm/mmu.h>
 #include <asm/fsl_law.h>
+#include "mp.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -123,6 +125,34 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 }
 #endif
 
+/* We run cpu_init_early_f in AS = 1 */
+void cpu_init_early_f(void)
+{
+       set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+               MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+               1, 0, BOOKE_PAGESZ_4K, 0);
+
+       /* set up CCSR if we want it moved */
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS)
+       {
+               u32 temp;
+
+               set_tlb(0, CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_DEFAULT,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       1, 1, BOOKE_PAGESZ_4K, 0);
+
+               temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT);
+               out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_PHYS >> 12);
+
+               temp = in_be32((volatile u32 *)CFG_CCSRBAR);
+       }
+#endif
+
+       init_laws();
+       invalidate_tlb(0);
+       init_tlbs();
+}
+
 /*
  * Breathe some life into the CPU...
  *
@@ -135,16 +165,15 @@ void cpu_init_f (void)
        volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
        extern void m8560_cpm_reset (void);
 
+       disable_tlb(14);
+       disable_tlb(15);
+
        /* Pointer is writable since we allocated a register for it */
        gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
 
        /* Clear initial global data */
        memset ((void *) gd, 0, sizeof (gd_t));
 
-#ifdef CONFIG_FSL_LAW
-       init_laws();
-#endif
-
 #ifdef CONFIG_CPM2
        config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR);
 #endif
@@ -243,7 +272,7 @@ int cpu_init_r(void)
        uint l2srbar;
 
        svr = get_svr();
-       ver = SVR_VER(svr);
+       ver = SVR_SOC_VER(svr);
 
        asm("msync;isync");
        cache_ctl = l2cache->l2ctl;
@@ -300,5 +329,8 @@ int cpu_init_r(void)
        qe_reset();
 #endif
 
+#if defined(CONFIG_MP)
+       setup_mp();
+#endif
        return 0;
 }