Merge branch 'socrates' of /home/wd/git/u-boot/projects

[oweals/u-boot.git] / cpu / mpc85xx / cpu_init.c

diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 888417f864baba3cdb94b724aa6363cc33168ac6..e3240b519ee8d5d44fe716d6a74edbcf88458565 100644 (file)
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -31,12 +31,38 @@
 #include <asm/processor.h>
 #include <ioports.h>
 #include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/fsl_law.h>
+#include "mp.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_QE
+extern qe_iop_conf_t qe_iop_conf_tab[];
+extern void qe_config_iopin(u8 port, u8 pin, int dir,
+                               int open_drain, int assign);
+extern void qe_init(uint qe_base);
+extern void qe_reset(void);
+
+static void config_qe_ioports(void)
+{
+       u8      port, pin;
+       int     dir, open_drain, assign;
+       int     i;
+
+       for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
+               port            = qe_iop_conf_tab[i].port;
+               pin             = qe_iop_conf_tab[i].pin;
+               dir             = qe_iop_conf_tab[i].dir;
+               open_drain      = qe_iop_conf_tab[i].open_drain;
+               assign          = qe_iop_conf_tab[i].assign;
+               qe_config_iopin(port, pin, dir, open_drain, assign);
+       }
+}
+#endif
 
 #ifdef CONFIG_CPM2
-static void config_8560_ioports (volatile immap_t * immr)
+void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 {
        int portnum;
 
@@ -76,7 +102,7 @@ static void config_8560_ioports (volatile immap_t * immr)
                }
 
                if (pmsk != 0) {
-                       volatile ioport_t *iop = ioport_addr (immr, portnum);
+                       volatile ioport_t *iop = ioport_addr (cpm, portnum);
                        uint tpmsk = ~pmsk;
 
                        /*
@@ -99,6 +125,34 @@ static void config_8560_ioports (volatile immap_t * immr)
 }
 #endif
 
+/* We run cpu_init_early_f in AS = 1 */
+void cpu_init_early_f(void)
+{
+       set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+               MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+               1, 0, BOOKE_PAGESZ_4K, 0);
+
+       /* set up CCSR if we want it moved */
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS)
+       {
+               u32 temp;
+
+               set_tlb(0, CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_DEFAULT,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       1, 1, BOOKE_PAGESZ_4K, 0);
+
+               temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT);
+               out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_PHYS >> 12);
+
+               temp = in_be32((volatile u32 *)CFG_CCSRBAR);
+       }
+#endif
+
+       init_laws();
+       invalidate_tlb(0);
+       init_tlbs();
+}
+
 /*
  * Breathe some life into the CPU...
  *
@@ -108,19 +162,20 @@ static void config_8560_ioports (volatile immap_t * immr)
 
 void cpu_init_f (void)
 {
-       volatile immap_t    *immap = (immap_t *)CFG_IMMR;
-       volatile ccsr_lbc_t *memctl = &immap->im_lbc;
+       volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
        extern void m8560_cpm_reset (void);
 
+       disable_tlb(14);
+       disable_tlb(15);
+
        /* Pointer is writable since we allocated a register for it */
        gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
 
        /* Clear initial global data */
        memset ((void *) gd, 0, sizeof (gd_t));
 
-
 #ifdef CONFIG_CPM2
-       config_8560_ioports(immap);
+       config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR);
 #endif
 
        /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
@@ -181,6 +236,11 @@ void cpu_init_f (void)
 #if defined(CONFIG_CPM2)
        m8560_cpm_reset();
 #endif
+#ifdef CONFIG_QE
+       /* Config QE ioports */
+       config_qe_ioports();
+#endif
+
 }
 
 
@@ -194,22 +254,25 @@ void cpu_init_f (void)
 
 int cpu_init_r(void)
 {
-       volatile immap_t    *immap = (immap_t *)CFG_IMMR;
-       volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
-
 #ifdef CONFIG_CLEAR_LAW0
+#ifdef CONFIG_FSL_LAW
+       disable_law(0);
+#else
+       volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
+
        /* clear alternate boot location LAW (used for sdram, or ddr bank) */
        ecm->lawar0 = 0;
 #endif
+#endif
 
 #if defined(CONFIG_L2_CACHE)
-       volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
+       volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
        volatile uint cache_ctl;
        uint svr, ver;
        uint l2srbar;
 
        svr = get_svr();
-       ver = SVR_VER(svr);
+       ver = SVR_SOC_VER(svr);
 
        asm("msync;isync");
        cache_ctl = l2cache->l2ctl;
@@ -217,7 +280,7 @@ int cpu_init_r(void)
        switch (cache_ctl & 0x30000000) {
        case 0x20000000:
                if (ver == SVR_8548 || ver == SVR_8548_E ||
-                   ver == SVR_8544) {
+                   ver == SVR_8544 || ver == SVR_8568_E) {
                        printf ("L2 cache 512KB:");
                        /* set L2E=1, L2I=1, & L2SRAM=0 */
                        cache_ctl = 0xc0000000;
@@ -260,6 +323,14 @@ int cpu_init_r(void)
 #else
        printf("L2 cache: disabled\n");
 #endif
+#ifdef CONFIG_QE
+       uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */
+       qe_init(qe_base);
+       qe_reset();
+#endif
 
+#if defined(CONFIG_MP)
+       setup_mp();
+#endif
        return 0;
 }