OMAP3: Fix timer handling to 1ms and CONFIG_SYS_HZ to 1000

[oweals/u-boot.git] / cpu / mpc85xx / cpu_init.c

diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 2d86547c203d704de572784b975c67fafeb5f31d..c98dd8da58fb829b983b7354bab108b608f60c31 100644 (file)
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -132,6 +132,12 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 /* We run cpu_init_early_f in AS = 1 */
 void cpu_init_early_f(void)
 {
+       /* Pointer is writable since we allocated a register for it */
+       gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+
+       /* Clear initial global data */
+       memset ((void *) gd, 0, sizeof (gd_t));
+
        set_tlb(0, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                1, 0, BOOKE_PAGESZ_4K, 0);
@@ -153,12 +159,6 @@ void cpu_init_early_f(void)
        }
 #endif
 
-       /* Pointer is writable since we allocated a register for it */
-       gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-
-       /* Clear initial global data */
-       memset ((void *) gd, 0, sizeof (gd_t));
-
        init_laws();
        invalidate_tlb(0);
        init_tlbs();
@@ -345,6 +345,19 @@ int cpu_init_r(void)
                asm("msync;isync");
                puts("enabled\n");
        }
+#elif defined(CONFIG_BACKSIDE_L2_CACHE)
+       u32 l2cfg0 = mfspr(SPRN_L2CFG0);
+
+       /* invalidate the L2 cache */
+       mtspr(SPRN_L2CSR0, L2CSR0_L2FI);
+       while (mfspr(SPRN_L2CSR0) & L2CSR0_L2FI)
+               ;
+
+       /* enable the cache */
+       mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
+
+       if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E)
+               printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
 #else
        puts("disabled\n");
 #endif