OMAP3: Fix timer handling to 1ms and CONFIG_SYS_HZ to 1000

[oweals/u-boot.git] / cpu / mpc85xx / cpu.c

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index b8f9125c73be1a0698a83b44e4966c14179de331..ef976a43fe8c013d2cdd25d73c7508d27a5212db 100644 (file)
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -30,6 +30,8 @@
 #include <watchdog.h>
 #include <command.h>
 #include <tsec.h>
+#include <netdev.h>
+#include <fsl_esdhc.h>
 #include <asm/cache.h>
 #include <asm/io.h>
 
@@ -59,8 +61,12 @@ struct cpu_type cpu_type_list [] = {
        CPU_TYPE_ENTRY(8567, 8567_E),
        CPU_TYPE_ENTRY(8568, 8568),
        CPU_TYPE_ENTRY(8568, 8568_E),
+       CPU_TYPE_ENTRY(8569, 8569),
+       CPU_TYPE_ENTRY(8569, 8569_E),
        CPU_TYPE_ENTRY(8572, 8572),
        CPU_TYPE_ENTRY(8572, 8572_E),
+       CPU_TYPE_ENTRY(P2020, P2020),
+       CPU_TYPE_ENTRY(P2020, P2020_E),
 };
 
 struct cpu_type *identify_cpu(u32 ver)
@@ -76,8 +82,6 @@ struct cpu_type *identify_cpu(u32 ver)
 int checkcpu (void)
 {
        sys_info_t sysinfo;
-       uint lcrr;              /* local bus clock ratio register */
-       uint clkdiv;            /* clock divider portion of lcrr */
        uint pvr, svr;
        uint fam;
        uint ver;
@@ -91,6 +95,7 @@ int checkcpu (void)
 #else
        u32 ddr_ratio = 0;
 #endif
+       int i;
 
        svr = get_svr();
        ver = SVR_SOC_VER(svr);
@@ -134,13 +139,22 @@ int checkcpu (void)
            puts("Unknown");
            break;
        }
+
+       if (PVR_MEM(pvr) == 0x03)
+               puts("MC");
+
        printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
 
        get_sys_info(&sysinfo);
 
-       puts("Clock Configuration:\n");
-       printf("       CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
-       printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
+       puts("Clock Configuration:");
+       for (i = 0; i < CONFIG_NUM_CPUS; i++) {
+               if (!(i & 3))
+                       printf ("\n       ");
+               printf("CPU%d:%-4s MHz, ",
+                               i,strmhz(buf1, sysinfo.freqProcessor[i]));
+       }
+       printf("\n       CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
 
        switch (ddr_ratio) {
        case 0x0:
@@ -160,30 +174,11 @@ int checkcpu (void)
                break;
        }
 
-#if defined(CONFIG_SYS_LBC_LCRR)
-       lcrr = CONFIG_SYS_LBC_LCRR;
-#else
-       {
-           volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-
-           lcrr = lbc->lcrr;
-       }
-#endif
-       clkdiv = lcrr & 0x0f;
-       if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
-#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
-    defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536)
-               /*
-                * Yes, the entire PQ38 family use the same
-                * bit-representation for twice the clock divider values.
-                */
-                clkdiv *= 2;
-#endif
-               printf("LBC:%-4s MHz\n",
-                      strmhz(buf1, sysinfo.freqSystemBus / clkdiv));
-       } else {
-               printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
-       }
+       if (sysinfo.freqLocalBus > LCRR_CLKDIV)
+               printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
+       else
+               printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
+                      sysinfo.freqLocalBus);
 
 #ifdef CONFIG_CPM2
        printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
@@ -379,9 +374,43 @@ void upmconfig (uint upm, uint * table, uint size)
  */
 int cpu_eth_init(bd_t *bis)
 {
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85xx_FEC)
+#if defined(CONFIG_ETHER_ON_FCC)
+       fec_initialize(bis);
+#endif
+#if defined(CONFIG_UEC_ETH1)
+       uec_initialize(0);
+#endif
+#if defined(CONFIG_UEC_ETH2)
+       uec_initialize(1);
+#endif
+#if defined(CONFIG_UEC_ETH3)
+       uec_initialize(2);
+#endif
+#if defined(CONFIG_UEC_ETH4)
+       uec_initialize(3);
+#endif
+#if defined(CONFIG_UEC_ETH5)
+       uec_initialize(4);
+#endif
+#if defined(CONFIG_UEC_ETH6)
+       uec_initialize(5);
+#endif
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
        tsec_standard_init(bis);
 #endif
 
        return 0;
 }
+
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_FSL_ESDHC
+       return fsl_esdhc_mmc_init(bis);
+#else
+       return 0;
+#endif
+}