#include <command.h>
#include <asm/cache.h>
+DECLARE_GLOBAL_DATA_PTR;
+
struct cpu_type {
char name[15];
u32 soc_ver;
get_sys_info(&sysinfo);
puts("Clock Configuration:\n");
- printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
- printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
-
+ printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
+ printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));
ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
switch (ddr_ratio) {
case 0x0:
- printf(" DDR:%4lu MHz, ", sysinfo.freqDDRBus / 2000000);
+ printf(" DDR:%4lu MHz (%lu MT/s data rate), ",
+ DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
break;
case 0x7:
- printf(" DDR:%4lu MHz (Synchronous), ", sysinfo.freqDDRBus / 2000000);
+ printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ",
+ DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000));
break;
default:
- printf(" DDR:%4lu MHz (Asynchronous), ", sysinfo.freqDDRBus / 2000000);
+ printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ",
+ DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
break;
}
clkdiv *= 2;
#endif
printf("LBC:%4lu MHz\n",
- sysinfo.freqSystemBus / 1000000 / clkdiv);
+ DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv);
} else {
printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
}
*/
unsigned long get_tbclk (void)
{
-
- sys_info_t sys_info;
-
- get_sys_info(&sys_info);
- return ((sys_info.freqSystemBus + 7L) / 8L);
+ return (gd->bus_clk + 4UL)/8UL;
}