Merge branch 'master' of /home/stefan/git/u-boot/u-boot
[oweals/u-boot.git] / cpu / mpc83xx / spd_sdram.c
index 97ac7bb3d95a0f00bafe5745c9e8b4eb43ca72e0..76f2474491a7b36441d5608e8bff64b95f62996b 100644 (file)
@@ -510,7 +510,7 @@ long int spd_sdram()
        ddr->timing_cfg_1 =
            (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |    /* PRETOACT */
             ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
-            (trcd_clk << 20 ) |                                /* ACTTORW */
+            (trcd_clk << 20 ) |                                /* ACTTORW */
             (caslat_ctrl << 16 ) |                             /* CASLAT */
             (trfc_low << 12 ) |                                /* REFEC */
             ((twr_clk & 0x07) << 8) |                          /* WRRREC */
@@ -601,7 +601,7 @@ long int spd_sdram()
        debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
 
        /* Check DIMM data bus width */
-       if (spd.dataw_lsb == 0x20) {
+       if (spd.dataw_lsb < 64) {
                if (spd.mem_type == SPD_MEMTYPE_DDR)
                        burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
                else
@@ -763,7 +763,7 @@ long int spd_sdram()
                sdram_cfg |= SDRAM_CFG_RD_EN;
 
        /* The DIMM is 32bit width */
-       if (spd.dataw_lsb == 0x20) {
+       if (spd.dataw_lsb < 64) {
                if (spd.mem_type == SPD_MEMTYPE_DDR)
                        sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
                if (spd.mem_type == SPD_MEMTYPE_DDR2)