ppc4xx: Consolidate pci_master_init() function

[oweals/u-boot.git] / cpu / mpc83xx / spd_sdram.c

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 42a4e675da46b66c663aa0005bb1442217eaa3c3..0f611804a0712e1b41db6e2b5da35b3d3d0293ee 100644 (file)
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -64,13 +64,6 @@ void board_add_ram_info(int use_default)
 }
 
 #ifdef CONFIG_SPD_EEPROM
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
-extern void dma_init(void);
-extern uint dma_check(void);
-extern int dma_xfer(void *dest, uint count, void *src);
-#endif
-
 #ifndef        CONFIG_SYS_READ_SPD
 #define CONFIG_SYS_READ_SPD    i2c_read
 #endif
@@ -219,7 +212,8 @@ long int spd_sdram()
        ddr->cs_config[0] = ( 1 << 31
                            | (odt_rd_cfg << 20)
                            | (odt_wr_cfg << 16)
-                           | (spd.nrow_addr - 12) << 8
+                           | ((spd.nbanks == 8 ? 1 : 0) << 14)
+                           | ((spd.nrow_addr - 12) << 8)
                            | (spd.ncol_addr - 8) );
        debug("\n");
        debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
@@ -231,8 +225,9 @@ long int spd_sdram()
                ddr->cs_config[1] = ( 1<<31
                                    | (odt_rd_cfg << 20)
                                    | (odt_wr_cfg << 16)
-                                   | (spd.nrow_addr-12) << 8
-                                   | (spd.ncol_addr-8) );
+                                   | ((spd.nbanks == 8 ? 1 : 0) << 14)
+                                   | ((spd.nrow_addr - 12) << 8)
+                                   | (spd.ncol_addr - 8) );
                debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
                debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
        }
@@ -242,7 +237,8 @@ long int spd_sdram()
        ddr->cs_config[2] = ( 1 << 31
                            | (odt_rd_cfg << 20)
                            | (odt_wr_cfg << 16)
-                           | (spd.nrow_addr - 12) << 8
+                           | ((spd.nbanks == 8 ? 1 : 0) << 14)
+                           | ((spd.nrow_addr - 12) << 8)
                            | (spd.ncol_addr - 8) );
        debug("\n");
        debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
@@ -254,8 +250,9 @@ long int spd_sdram()
                ddr->cs_config[3] = ( 1<<31
                                    | (odt_rd_cfg << 20)
                                    | (odt_wr_cfg << 16)
-                                   | (spd.nrow_addr-12) << 8
-                                   | (spd.ncol_addr-8) );
+                                   | ((spd.nbanks == 8 ? 1 : 0) << 14)
+                                   | ((spd.nrow_addr - 12) << 8)
+                                   | (spd.ncol_addr - 8) );
                debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
                debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
        }
@@ -319,7 +316,20 @@ long int spd_sdram()
        ddrc_clk = gd->mem_clk / 1000000;
        effective_data_rate = 0;
 
-       if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
+       if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */
+               if (spd.cas_lat & 0x08)
+                       caslat = 3;
+               else
+                       caslat = 4;
+               if (ddrc_clk <= 460 && ddrc_clk > 350)
+                       effective_data_rate = 400;
+               else if (ddrc_clk <=350 && ddrc_clk > 280)
+                       effective_data_rate = 333;
+               else if (ddrc_clk <= 280 && ddrc_clk > 230)
+                       effective_data_rate = 266;
+               else
+                       effective_data_rate = 200;
+       } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
                if (ddrc_clk <= 460 && ddrc_clk > 350) {
                        /* DDR controller clk at 350~460 */
                        effective_data_rate = 400; /* 5ns */
@@ -466,6 +476,8 @@ long int spd_sdram()
        } else {
                twr_clk = picos_to_clk(spd.twr * 250);
                twtr_clk = picos_to_clk(spd.twtr * 250);
+               if (twtr_clk < 2)
+                       twtr_clk = 2;
        }
 
        /*
@@ -529,7 +541,7 @@ long int spd_sdram()
        if (spd.mem_type == SPD_MEMTYPE_DDR2
            && (odt_wr_cfg || odt_rd_cfg)
            && (caslat < 4)) {
-               add_lat = trcd_clk - 1;
+               add_lat = 4 - caslat;
                if ((add_lat + caslat) < 4) {
                        add_lat = 0;
                }
@@ -566,6 +578,9 @@ long int spd_sdram()
 
                /* Convert SPD value from quarter nanos to picos. */
                trtp_clk = picos_to_clk(spd.trtp * 250);
+               if (trtp_clk < 2)
+                       trtp_clk = 2;
+               trtp_clk += add_lat;
 
                cke_min_clk = 3;        /* By the book. */
                four_act = picos_to_clk(37500); /* By the book. 1k pages? */
@@ -579,7 +594,9 @@ long int spd_sdram()
        if (spd.mem_type == SPD_MEMTYPE_DDR2) {
                if (effective_data_rate == 266) {
                        cpo = 0x4;              /* READ_LAT + 1/2 */
-               } else if (effective_data_rate == 333 || effective_data_rate == 400) {
+               } else if (effective_data_rate == 333) {
+                       cpo = 0x6;              /* READ_LAT + 1 */
+               } else if (effective_data_rate == 400) {
                        cpo = 0x7;              /* READ_LAT + 5/4 */
                } else {
                        /* Automatic calibration */
@@ -806,7 +823,7 @@ long int spd_sdram()
 }
 #endif /* CONFIG_SPD_EEPROM */
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 /*
  * Use timebase counter, get_timer() is not availabe
  * at this point of initialization yet.
@@ -839,7 +856,6 @@ static __inline__ unsigned long get_tbms (void)
 /*
  * Initialize all of memory for ECC, then enable errors.
  */
-/* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
 void ddr_enable_ecc(unsigned int dram_size)
 {
        volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
@@ -848,46 +864,21 @@ void ddr_enable_ecc(unsigned int dram_size)
        register u64 *p;
        register uint size;
        unsigned int pattern[2];
-#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
-       uint i;
-#endif
+
        icache_enable();
        t_start = get_tbms();
        pattern[0] = 0xdeadbeef;
        pattern[1] = 0xdeadbeef;
 
-#if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
+#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
+       dma_meminit(pattern[0], dram_size);
+#else
        debug("ddr init: CPU FP write method\n");
        size = dram_size;
        for (p = 0; p < (u64*)(size); p++) {
                ppcDWstore((u32*)p, pattern);
        }
        __asm__ __volatile__ ("sync");
-#else
-       debug("ddr init: DMA method\n");
-       size = 0x2000;
-       for (p = 0; p < (u64*)(size); p++) {
-               ppcDWstore((u32*)p, pattern);
-       }
-       __asm__ __volatile__ ("sync");
-
-       /* Initialise DMA for direct transfer */
-       dma_init();
-       /* Start DMA to transfer */
-       dma_xfer((uint *)0x2000, 0x2000, (uint *)0); /* 8K */
-       dma_xfer((uint *)0x4000, 0x4000, (uint *)0); /* 16K */
-       dma_xfer((uint *)0x8000, 0x8000, (uint *)0); /* 32K */
-       dma_xfer((uint *)0x10000, 0x10000, (uint *)0); /* 64K */
-       dma_xfer((uint *)0x20000, 0x20000, (uint *)0); /* 128K */
-       dma_xfer((uint *)0x40000, 0x40000, (uint *)0); /* 256K */
-       dma_xfer((uint *)0x80000, 0x80000, (uint *)0); /* 512K */
-       dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
-       dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
-       dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
-
-       for (i = 1; i < dram_size / 0x800000; i++) {
-               dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
-       }
 #endif
 
        t_end = get_tbms();