ppc4xx: Add 405GPr based MCU25 board config file

[oweals/u-boot.git] / cpu / mpc83xx / spd_sdram.c

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index ee2d0385e457b6bcc8b720024aba63e3b8ef5096..0acca4771783dc30f6a0953968732828f4523915 100644 (file)
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2006 Freescale Semiconductor, Inc.
+ * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -198,6 +198,7 @@ long int spd_sdram()
        if(spd.mem_type == SPD_MEMTYPE_DDR2) {
                immap->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
        }
+       udelay(50000);
 #endif
 
        /*
@@ -573,10 +574,10 @@ long int spd_sdram()
         */
        cpo = 0;
        if (spd.mem_type == SPD_MEMTYPE_DDR2) {
-               if (effective_data_rate == 266 || effective_data_rate == 333) {
+               if (effective_data_rate == 266) {
+                       cpo = 0x4;              /* READ_LAT + 1/2 */
+               } else if (effective_data_rate == 333 || effective_data_rate == 400) {
                        cpo = 0x7;              /* READ_LAT + 5/4 */
-               } else if (effective_data_rate == 400) {
-                       cpo = 0x9;              /* READ_LAT + 7/4 */
                } else {
                        /* Automatic calibration */
                        cpo = 0x1f;
@@ -705,9 +706,11 @@ long int spd_sdram()
         * SDRAM Cfg 2
         */
        odt_cfg = 0;
+#ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
        if (odt_rd_cfg | odt_wr_cfg) {
                odt_cfg = 0x2;          /* ODT to IOs during reads */
        }
+#endif
        if (spd.mem_type == SPD_MEMTYPE_DDR2) {
                ddr->sdram_cfg2 = (0
                            | (0 << 26) /* True DQS */