#define cfg_write(val, addr, type, op) \
do { op((type *)(addr), (val)); } while (0)
+#define cfg_read_err(val) do { *val = -1; } while (0)
+#define cfg_write_err(val) do { } while (0)
+
#define PCIE_OP(rw, size, type, op) \
static int pcie_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, \
int ret; \
\
ret = mpc83xx_pcie_remap_cfg(hose, dev); \
- if (ret) \
- return ret; \
+ if (ret) { \
+ cfg_##rw##_err(val); \
+ return ret; \
+ } \
cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \
return 0; \
}
{
extern void disable_addr_trans(void); /* start.S */
static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
- static int max_bus;
struct pci_controller *hose = &pcie_hose[bus];
int i;
hose->regions[i].bus_start = 0;
hose->regions[i].phys_start = 0;
hose->regions[i].size = gd->ram_size;
- hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
+ hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
i = hose->region_count++;
hose->regions[i].bus_start = CONFIG_SYS_IMMR;
hose->regions[i].phys_start = CONFIG_SYS_IMMR;
hose->regions[i].size = 0x100000;
- hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
+ hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
- hose->first_busno = max_bus;
+ hose->first_busno = pci_last_busno() + 1;
hose->last_busno = 0xff;
if (bus == 0)
* Hose scan.
*/
hose->last_busno = pci_hose_scan(hose);
- max_bus = hose->last_busno + 1;
}
#else