#include <mpc83xx.h>
#include <asm/processor.h>
#include <libfdt.h>
+#include <tsec.h>
+#include <netdev.h>
+#include <fsl_esdhc.h>
+#ifdef CONFIG_BOOTCOUNT_LIMIT
+#include <asm/immap_qe.h>
+#include <asm/io.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
CPU_TYPE_ENTRY(8379),
};
- immr = (immap_t *)CFG_IMMR;
+ immr = (immap_t *)CONFIG_SYS_IMMR;
puts("CPU: ");
* The 'dummy' variable is used to increment the MAD. 'dummy' is
* supposed to be a pointer to the memory of the device being
* programmed by the UPM. The data in the MDR is written into
- * memory and the MAD is incremented every time there's a read
- * from 'dummy'. Unfortunately, the current prototype for this
+ * memory and the MAD is incremented every time there's a write
+ * to 'dummy'. Unfortunately, the current prototype for this
* function doesn't allow for passing the address of this
* device, and changing the prototype will break a number lots
* of other code, so we need to use a round-about way of finding
*/
void upmconfig (uint upm, uint *table, uint size)
{
-#if defined(CONFIG_MPC834X)
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- volatile lbus83xx_t *lbus = &immap->lbus;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ volatile fsl_lbus_t *lbus = &immap->lbus;
volatile uchar *dummy = NULL;
const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
for (i = 0; i < size; i++) {
lbus->mdr = table[i];
__asm__ __volatile__ ("sync");
- *dummy; /* Write the value to memory and increment MAD */
+ *dummy = 0; /* Write the value to memory and increment MAD */
__asm__ __volatile__ ("sync");
+ while(((*mxmr & 0x3f) != ((i + 1) & 0x3f)));
}
/* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
*mxmr &= 0xCFFFFFC0;
-#else
- printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
- hang();
-#endif
}
ulong addr;
#endif
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
#ifdef MPC83xx_RESET
/* Interrupts and MMU off */
* Trying to execute the next instruction at a non-existing address
* should cause a machine check, resulting in reset
*/
- addr = CFG_RESET_ADDRESS;
+ addr = CONFIG_SYS_RESET_ADDRESS;
printf("resetting the board.");
printf("\n");
int re_enable = disable_interrupts();
/* Reset the 83xx watchdog */
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
immr->wdt.swsrr = 0x556c;
immr->wdt.swsrr = 0xaa39;
}
#endif
-#if defined(CONFIG_DDR_ECC)
-void dma_init(void)
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile dma83xx_t *dma = &immap->dma;
- volatile u32 status = swab32(dma->dmasr0);
- volatile u32 dmamr0 = swab32(dma->dmamr0);
-
- debug("DMA-init\n");
-
- /* initialize DMASARn, DMADAR and DMAABCRn */
- dma->dmadar0 = (u32)0;
- dma->dmasar0 = (u32)0;
- dma->dmabcr0 = 0;
-
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
-
- /* clear CS bit */
- dmamr0 &= ~DMA_CHANNEL_START;
- dma->dmamr0 = swab32(dmamr0);
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
-
- /* while the channel is busy, spin */
- while(status & DMA_CHANNEL_BUSY) {
- status = swab32(dma->dmasr0);
- }
+#if defined(CONFIG_UEC_ETH)
+ uec_standard_init(bis);
+#endif
- debug("DMA-init end\n");
+#if defined(CONFIG_TSEC_ENET)
+ tsec_standard_init(bis);
+#endif
+ return 0;
}
-uint dma_check(void)
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile dma83xx_t *dma = &immap->dma;
- volatile u32 status = swab32(dma->dmasr0);
- volatile u32 byte_count = swab32(dma->dmabcr0);
-
- /* while the channel is busy, spin */
- while (status & DMA_CHANNEL_BUSY) {
- status = swab32(dma->dmasr0);
- }
-
- if (status & DMA_CHANNEL_TRANSFER_ERROR) {
- printf ("DMA Error: status = %x @ %d\n", status, byte_count);
- }
-
- return status;
+#ifdef CONFIG_FSL_ESDHC
+ return fsl_esdhc_mmc_init(bis);
+#else
+ return 0;
+#endif
}
-int dma_xfer(void *dest, u32 count, void *src)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile dma83xx_t *dma = &immap->dma;
- volatile u32 dmamr0;
+#ifdef CONFIG_BOOTCOUNT_LIMIT
- /* initialize DMASARn, DMADAR and DMAABCRn */
- dma->dmadar0 = swab32((u32)dest);
- dma->dmasar0 = swab32((u32)src);
- dma->dmabcr0 = swab32(count);
-
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
+#if !defined(CONFIG_MPC8360)
+#error "CONFIG_BOOTCOUNT_LIMIT only for MPC8360 implemented"
+#endif
- /* init direct transfer, clear CS bit */
- dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
- DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
- DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
+#if !defined(CONFIG_BOOTCOUNT_ADDR)
+#define CONFIG_BOOTCOUNT_ADDR (0x110000 + QE_MURAM_SIZE - 2 * sizeof(unsigned long))
+#endif
- dma->dmamr0 = swab32(dmamr0);
+#include <asm/io.h>
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
+void bootcount_store (ulong a)
+{
+ void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR);
+ out_be32 (reg, a);
+ out_be32 (reg + 4, BOOTCOUNT_MAGIC);
+}
- /* set CS to start DMA transfer */
- dmamr0 |= DMA_CHANNEL_START;
- dma->dmamr0 = swab32(dmamr0);
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
+ulong bootcount_load (void)
+{
+ void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR);
- return ((int)dma_check());
+ if (in_be32 (reg + 4) != BOOTCOUNT_MAGIC)
+ return 0;
+ else
+ return in_be32 (reg);
}
-#endif /*CONFIG_DDR_ECC*/
+#endif /* CONFIG_BOOTCOUNT_LIMIT */