#include <asm/processor.h>
#include <libfdt.h>
#include <tsec.h>
+#include <netdev.h>
+#include <fsl_esdhc.h>
+#ifdef CONFIG_BOOTCOUNT_LIMIT
+#include <asm/immap_qe.h>
+#include <asm/io.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
void upmconfig (uint upm, uint *table, uint size)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile lbus83xx_t *lbus = &immap->lbus;
+ volatile fsl_lbus_t *lbus = &immap->lbus;
volatile uchar *dummy = NULL;
const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
}
#endif
-#if defined(CONFIG_DDR_ECC)
-void dma_init(void)
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile dma83xx_t *dma = &immap->dma;
- volatile u32 status = swab32(dma->dmasr0);
- volatile u32 dmamr0 = swab32(dma->dmamr0);
-
- debug("DMA-init\n");
-
- /* initialize DMASARn, DMADAR and DMAABCRn */
- dma->dmadar0 = (u32)0;
- dma->dmasar0 = (u32)0;
- dma->dmabcr0 = 0;
-
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
-
- /* clear CS bit */
- dmamr0 &= ~DMA_CHANNEL_START;
- dma->dmamr0 = swab32(dmamr0);
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
-
- /* while the channel is busy, spin */
- while(status & DMA_CHANNEL_BUSY) {
- status = swab32(dma->dmasr0);
- }
+#if defined(CONFIG_UEC_ETH)
+ uec_standard_init(bis);
+#endif
- debug("DMA-init end\n");
+#if defined(CONFIG_TSEC_ENET)
+ tsec_standard_init(bis);
+#endif
+ return 0;
}
-uint dma_check(void)
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile dma83xx_t *dma = &immap->dma;
- volatile u32 status = swab32(dma->dmasr0);
- volatile u32 byte_count = swab32(dma->dmabcr0);
-
- /* while the channel is busy, spin */
- while (status & DMA_CHANNEL_BUSY) {
- status = swab32(dma->dmasr0);
- }
-
- if (status & DMA_CHANNEL_TRANSFER_ERROR) {
- printf ("DMA Error: status = %x @ %d\n", status, byte_count);
- }
-
- return status;
+#ifdef CONFIG_FSL_ESDHC
+ return fsl_esdhc_mmc_init(bis);
+#else
+ return 0;
+#endif
}
-int dma_xfer(void *dest, u32 count, void *src)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile dma83xx_t *dma = &immap->dma;
- volatile u32 dmamr0;
+#ifdef CONFIG_BOOTCOUNT_LIMIT
- /* initialize DMASARn, DMADAR and DMAABCRn */
- dma->dmadar0 = swab32((u32)dest);
- dma->dmasar0 = swab32((u32)src);
- dma->dmabcr0 = swab32(count);
-
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
-
- /* init direct transfer, clear CS bit */
- dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
- DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
- DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
+#if !defined(CONFIG_MPC8360)
+#error "CONFIG_BOOTCOUNT_LIMIT only for MPC8360 implemented"
+#endif
- dma->dmamr0 = swab32(dmamr0);
+#if !defined(CONFIG_BOOTCOUNT_ADDR)
+#define CONFIG_BOOTCOUNT_ADDR (0x110000 + QE_MURAM_SIZE - 2 * sizeof(unsigned long))
+#endif
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
+#include <asm/io.h>
- /* set CS to start DMA transfer */
- dmamr0 |= DMA_CHANNEL_START;
- dma->dmamr0 = swab32(dmamr0);
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
-
- return ((int)dma_check());
+void bootcount_store (ulong a)
+{
+ void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR);
+ out_be32 (reg, a);
+ out_be32 (reg + 4, BOOTCOUNT_MAGIC);
}
-#endif /*CONFIG_DDR_ECC*/
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
+ulong bootcount_load (void)
{
-#if defined(CONFIG_TSEC_ENET)
- tsec_standard_init(bis);
-#endif
+ void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR);
- return 0;
+ if (in_be32 (reg + 4) != BOOTCOUNT_MAGIC)
+ return 0;
+ else
+ return in_be32 (reg);
}
+#endif /* CONFIG_BOOTCOUNT_LIMIT */