mpc85xx: Add support for the MPC8536

[oweals/u-boot.git] / cpu / mpc8260 / pci.c

diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
index 1edd6fb8ddd0ba138c462516d145f0ca2acd276a..82303644b2be6df407b296992f3c251f90e839eb 100644 (file)
--- a/cpu/mpc8260/pci.c
+++ b/cpu/mpc8260/pci.c
@@ -33,6 +33,10 @@
 #include <mpc8260.h>
 #include <asm/m8260_pci.h>
 #include <asm/io.h>
+#ifdef CONFIG_OF_LIBFDT
+#include <libfdt.h>
+#include <fdt_support.h>
+#endif
 
 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
 DECLARE_GLOBAL_DATA_PTR;
@@ -275,22 +279,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
                                  | SIUMCR_BCTLC00
                                  | SIUMCR_MMR11;
 #elif defined(CONFIG_TQM8272)
-#if 0
-       immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
-                                               ~SIUMCR_LBPC11 &
-                                               ~SIUMCR_CS10PC11 &
-                                               ~SIUMCR_LBPC11) |
-                                       SIUMCR_LBPC01 |
-                                       SIUMCR_CS10PC01 |
-                                       SIUMCR_APPC10;
-#else
-#if 0
-       immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr |
-                                       SIUMCR_APPC10);
-#else
-       immap->im_siu_conf.sc_siumcr = 0x88000000;
-#endif
-#endif
+/* nothing to do for this Board here */
 #else
        /*
         * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
@@ -304,7 +293,6 @@ void pci_mpc8250_init (struct pci_controller *hose)
                                        SIUMCR_CS10PC01 |
                                        SIUMCR_APPC10;
 #endif
-printf("%s siumcr: %x\n", __FUNCTION__, immap->im_siu_conf.sc_siumcr);
 
        /* Make PCI lowest priority */
        /* Each 4 bits is a device bus request  and the MS 4bits
@@ -465,4 +453,12 @@ printf("%s siumcr: %x\n", __FUNCTION__, immap->im_siu_conf.sc_siumcr);
        immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
 }
 
+#if defined(CONFIG_OF_LIBFDT)
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+       do_fixup_by_prop_u32(blob, "device_type", "pci", 4,
+               "clock-frequency", gd->pci_clk, 1);
+}
+#endif
+
 #endif /* CONFIG_PCI */