Merge with git://www.denx.de/git/u-boot.git

[oweals/u-boot.git] / cpu / mpc824x / cpu_init.c

diff --git a/cpu/mpc824x/cpu_init.c b/cpu/mpc824x/cpu_init.c
index 08f5c4ab13a384cb2afb7ddde6564e251edb2354..7871031b9709610ac9fa805992b1260af8172902 100644 (file)
--- a/cpu/mpc824x/cpu_init.c
+++ b/cpu/mpc824x/cpu_init.c
@@ -90,7 +90,7 @@ cpu_init_f (void)
 #endif
 
        CONFIG_WRITE_BYTE(PCLSR, 0x8);  /* set PCI cache line size */
-
+       CONFIG_WRITE_BYTE (PLTR, 0x40); /* set PCI latency timer */
        /*
        * Note that although this bit is cleared after a hard reset, it
        * must be explicitly set and then cleared by software during
@@ -106,9 +106,24 @@ cpu_init_f (void)
        CONFIG_READ_BYTE(AMBOR,val);
        CONFIG_WRITE_BYTE(AMBOR,val|0x1);
 
+#if 0
+       /*
+        * The following bug only affects older (XPC8245) processors.
+        * DMA transfers initiated by external devices get corrupted due
+        * to a hardware scheduling problem.
+        *
+        * The effect is:
+        * when transferring X words, the first 32 words are transferred
+        * OK, the next 3 x 32 words are 'old' data (from previous DMA)
+        * while the rest of the X words is xferred fine.
+        *
+        * Disabling 3 of the 4 32 word hardware buffers solves the problem
+        * with no significant performance loss.
+        */
+
        CONFIG_READ_BYTE(PCMBCR,val);
        /* in order not to corrupt data which is being read over the PCI bus
-       * with the PPC as master, we need to reduce the number of PCMRBs to 1,
+       * with the PPC as slave, we need to reduce the number of PCMRBs to 1,
        * 4.11 in the  processor user manual
        * */
 
@@ -117,6 +132,8 @@ cpu_init_f (void)
 #else
        CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */
        CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */
+       /* default, 4 PCMRBs are used */
+#endif
 #endif
 #endif