Merge git://www.denx.de/git/u-boot

[oweals/u-boot.git] / cpu / mpc5xx / start.S

diff --git a/cpu/mpc5xx/start.S b/cpu/mpc5xx/start.S
index 548ec99e2c8499de2ea169486f55a5494f01b00f..0637003ce29916b0fdd8ffd2b83a5a1e2335e41b 100644 (file)
--- a/cpu/mpc5xx/start.S
+++ b/cpu/mpc5xx/start.S
@@ -117,6 +117,29 @@ boot_warm:
        mtspr   COUNTA, r0
        mtspr   COUNTB, r0
 
+#if defined(CONFIG_PATI)
+       /* the external flash access on PATI fails if programming the PLL to 40MHz.
+        * Copy the PLL programming code to the internal RAM and execute it
+        *----------------------------------------------------------------------*/
+       lis     r3, CFG_MONITOR_BASE@h
+       ori     r3, r3, CFG_MONITOR_BASE@l
+       addi    r3, r3, pll_prog_code_start - _start + EXC_OFF_SYS_RESET
+
+       lis     r4, CFG_INIT_RAM_ADDR@h
+       ori     r4, r4, CFG_INIT_RAM_ADDR@l
+       mtlr    r4
+       addis   r5,0,0x0
+       ori     r5,r5,((pll_prog_code_end - pll_prog_code_start) >>2)
+       mtctr   r5
+       addi    r3, r3, -4
+       addi    r4, r4, -4
+0:
+       lwzu    r0,4(r3)
+       stwu    r0,4(r4)
+       bdnz    0b                /* copy loop */
+       blrl
+#endif
+
        /*
         * Calculate absolute address in FLASH and jump there
         *----------------------------------------------------------------------*/
@@ -132,7 +155,7 @@ in_flash:
        /* Initialize some SPRs that are hard to access from C                  */
        /*----------------------------------------------------------------------*/
 
-       lis     r3, CFG_IMMR@h                  /* Pass IMMR as arg1 to C routine */
+       lis     r3, CFG_IMMR@h                  /* Pass IMMR as arg1 to C routine */
        lis     r2, CFG_INIT_SP_ADDR@h
        ori     r1, r2, CFG_INIT_SP_ADDR@l      /* Set up the stack in internal SRAM */
        /* Note: R0 is still 0 here */
@@ -187,7 +210,7 @@ _start_of_vectors:
 /* Alignment exception. */
        . = 0x600
 Alignment:
-       EXCEPTION_PROLOG
+       EXCEPTION_PROLOG(SRR0, SRR1)
        mfspr   r4,DAR
        stw     r4,_DAR(r21)
        mfspr   r5,DSISR
@@ -205,7 +228,7 @@ Alignment:
 /* Program check exception */
        . = 0x700
 ProgramCheck:
-       EXCEPTION_PROLOG
+       EXCEPTION_PROLOG(SRR0, SRR1)
        addi    r3,r1,STACK_FRAME_OVERHEAD
        li      r20,MSR_KERNEL
        rlwimi  r20,r23,0,16,16         /* copy EE bit from saved MSR */
@@ -553,3 +576,28 @@ trap_reloc:
        isync
 
        blr
+
+
+#if defined(CONFIG_PATI)
+/* Program the PLL */
+pll_prog_code_start:
+       lis     r4, (CFG_IMMR + 0x002fc384)@h
+       ori     r4, r4, (CFG_IMMR + 0x002fc384)@l
+       lis     r3, (0x55ccaa33)@h
+       ori     r3, r3, (0x55ccaa33)@l
+       stw     r3, 0(r4)
+       lis     r4, (CFG_IMMR + 0x002fc284)@h
+       ori     r4, r4, (CFG_IMMR + 0x002fc284)@l
+       lis     r3, CFG_PLPRCR@h
+       ori     r3, r3, CFG_PLPRCR@l
+       stw     r3, 0(r4)
+       addis   r3,0,0x0
+       ori     r3,r3,0xA000
+       mtctr   r3
+..spinlp:
+  bdnz    ..spinlp                /* spin loop */
+       blr
+pll_prog_code_end:
+       nop
+       blr
+#endif