[MIPS] cpu/mips/cache.S: Add dcache_enable

[oweals/u-boot.git] / cpu / mips / start.S

diff --git a/cpu/mips/start.S b/cpu/mips/start.S
index c92b16278267200d208cc649fa1d7722628d92da..6e1a78ceac44175b1401a136ad0005e4494115b2 100644 (file)
--- a/cpu/mips/start.S
+++ b/cpu/mips/start.S
@@ -27,6 +27,30 @@
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>
 
+       /*
+        * For the moment disable interrupts, mark the kernel mode and
+        * set ST0_KX so that the CPU does not spit fire when using
+        * 64-bit addresses.
+        */
+       .macro  setup_c0_status set clr
+       .set    push
+       mfc0    t0, CP0_STATUS
+       or      t0, ST0_CU0 | \set | 0x1f | \clr
+       xor     t0, 0x1f | \clr
+       mtc0    t0, CP0_STATUS
+       .set    noreorder
+       sll     zero, 3                         # ehb
+       .set    pop
+       .endm
+
+       .macro  setup_c0_status_reset
+#ifdef CONFIG_64BIT
+       setup_c0_status ST0_KX 0
+#else
+       setup_c0_status 0 0
+#endif
+       .endm
+
 #define RVECENT(f,n) \
    b f; nop
 #define XVECENT(f,bev) \
@@ -211,19 +235,11 @@ reset:
        mtc0    zero, CP0_WATCHLO
        mtc0    zero, CP0_WATCHHI
 
-       /* STATUS register */
-#ifdef  CONFIG_TB0229
-       li      k0, ST0_CU0
-#else
-       mfc0    k0, CP0_STATUS
-#endif
-       li      k1, ~ST0_IE
-       and     k0, k1
-       mtc0    k0, CP0_STATUS
-
-       /* CAUSE register */
+       /* WP(Watch Pending), SW0/1 should be cleared. */
        mtc0    zero, CP0_CAUSE
 
+       setup_c0_status_reset
+
        /* Init Timer */
        mtc0    zero, CP0_COUNT
        mtc0    zero, CP0_COMPARE
@@ -240,14 +256,6 @@ reset:
 1:
        lw      gp, 0(ra)
 
-#ifdef CONFIG_INCA_IP
-       /* Disable INCA-IP Watchdog.
-        */
-       la      t9, disable_incaip_wdt
-       jalr    t9
-       nop
-#endif
-
        /* Initialize any external memory.
         */
        la      t9, lowlevel_init
@@ -267,16 +275,18 @@ reset:
 
        /* Set up temporary stack.
         */
+#ifdef CFG_INIT_RAM_LOCK_MIPS
        li      a0, CFG_INIT_SP_OFFSET
        la      t9, mips_cache_lock
        jalr    t9
        nop
+#endif
 
        li      t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
        la      sp, 0(t0)
 
        la      t9, board_init_f
-       j       t9
+       jr      t9
        nop
 
 /*
@@ -332,7 +342,7 @@ relocate_code:
        /* Jump to where we've relocated ourselves.
         */
        addi    t0, a2, in_ram - _start
-       j       t0
+       jr      t0
        nop
 
        .gpword _GLOBAL_OFFSET_TABLE_   /* _GLOBAL_OFFSET_TABLE_ - _gp  */
@@ -377,7 +387,7 @@ in_ram:
 
        move    a0, a1
        la      t9, board_init_r
-       j       t9
+       jr      t9
        move    a1, a2          /* delay slot                   */
 
        .end    relocate_code