Merge branch 'master' of git://git.denx.de/u-boot-net

[oweals/u-boot.git] / cpu / mips / cpu.c

diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c
index 7559ac657f40384dded344006b8a7076e5b68c0e..d5a16047de9500fd6c62815dd3a437d68f3ce636 100644 (file)
--- a/cpu/mips/cpu.c
+++ b/cpu/mips/cpu.c
@@ -23,32 +23,90 @@
 
 #include <common.h>
 #include <command.h>
-#include <asm/inca-ip.h>
+#include <netdev.h>
 #include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+#include <asm/reboot.h>
+
+#define cache_op(op,addr)                                              \
+       __asm__ __volatile__(                                           \
+       "       .set    push                                    \n"     \
+       "       .set    noreorder                               \n"     \
+       "       .set    mips3\n\t                               \n"     \
+       "       cache   %0, %1                                  \n"     \
+       "       .set    pop                                     \n"     \
+       :                                                               \
+       : "i" (op), "R" (*(unsigned char *)(addr)))
+
+void __attribute__((weak)) _machine_restart(void)
+{
+}
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-#if defined(CONFIG_INCA_IP)
-       *INCA_IP_WDT_RST_REQ = 0x3f;
-#elif defined(CONFIG_PURPLE) || defined(CONFIG_TB0229)
-       void (*f)(void) = (void *) 0xbfc00000;
+       _machine_restart();
 
-       f();
-#endif
        fprintf(stderr, "*** reset failed ***\n");
        return 0;
 }
 
 void flush_cache(ulong start_addr, ulong size)
 {
+       unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+       unsigned long addr = start_addr & ~(lsize - 1);
+       unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+
+       while (1) {
+               cache_op(Hit_Writeback_Inv_D, addr);
+               cache_op(Hit_Invalidate_I, addr);
+               if (addr == aend)
+                       break;
+               addr += lsize;
+       }
+}
+
+void flush_dcache_range(ulong start_addr, ulong stop)
+{
+       unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+       unsigned long addr = start_addr & ~(lsize - 1);
+       unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+       while (1) {
+               cache_op(Hit_Writeback_Inv_D, addr);
+               if (addr == aend)
+                       break;
+               addr += lsize;
+       }
+}
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+       unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+       unsigned long addr = start_addr & ~(lsize - 1);
+       unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+       while (1) {
+               cache_op(Hit_Invalidate_D, addr);
+               if (addr == aend)
+                       break;
+               addr += lsize;
+       }
 }
 
 void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
 {
-       write_32bit_cp0_register(CP0_ENTRYLO0, low0);
-       write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
-       write_32bit_cp0_register(CP0_ENTRYLO1, low1);
-       write_32bit_cp0_register(CP0_ENTRYHI, hi);
-       write_32bit_cp0_register(CP0_INDEX, index);
+       write_c0_entrylo0(low0);
+       write_c0_pagemask(pagemask);
+       write_c0_entrylo1(low1);
+       write_c0_entryhi(hi);
+       write_c0_index(index);
        tlb_write_indexed();
 }
+
+int cpu_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SOC_AU1X00
+       au1x00_enet_initialize(bis);
+#endif
+       return 0;
+}