Merge branch 'master' of git://www.denx.de/git/u-boot-at91

[oweals/u-boot.git] / cpu / mcf532x / cpu_init.c

diff --git a/cpu/mcf532x/cpu_init.c b/cpu/mcf532x/cpu_init.c
index 32711a17443cd4aa2072c0cabc5e5d80ae691ba9..93086f74bf014a768433ef9e0937290ad73197e5 100644 (file)
--- a/cpu/mcf532x/cpu_init.c
+++ b/cpu/mcf532x/cpu_init.c
@@ -60,22 +60,8 @@ void cpu_init_f(void)
        scm2->pacrg = 0;
        scm1->pacrh = 0;
 
-       /* Setup Ports: */
-       switch (CFG_UART_PORT) {
-       case 0:
-               gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
-               break;
-       case 1:
-               gpio->par_uart =
-                   (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
-               break;
-       case 2:
-               gpio->par_uart = (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
-               break;
-       }
-
        /* Port configuration */
-       gpio->par_cs = 0x3E;
+       gpio->par_cs = 0;
 
 #if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
        fbcs->csar0 = CFG_CS0_BASE;
@@ -85,35 +71,44 @@ void cpu_init_f(void)
 
 #if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
        /* Latch chipselect */
+       gpio->par_cs |= GPIO_PAR_CS1;
        fbcs->csar1 = CFG_CS1_BASE;
        fbcs->cscr1 = CFG_CS1_CTRL;
        fbcs->csmr1 = CFG_CS1_MASK;
 #endif
 
 #if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
+       gpio->par_cs |= GPIO_PAR_CS2;
        fbcs->csar2 = CFG_CS2_BASE;
        fbcs->cscr2 = CFG_CS2_CTRL;
        fbcs->csmr2 = CFG_CS2_MASK;
 #endif
 
 #if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
+       gpio->par_cs |= GPIO_PAR_CS3;
        fbcs->csar3 = CFG_CS3_BASE;
        fbcs->cscr3 = CFG_CS3_CTRL;
        fbcs->csmr3 = CFG_CS3_MASK;
 #endif
 
 #if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
+       gpio->par_cs |= GPIO_PAR_CS4;
        fbcs->csar4 = CFG_CS4_BASE;
        fbcs->cscr4 = CFG_CS4_CTRL;
        fbcs->csmr4 = CFG_CS4_MASK;
 #endif
 
 #if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
+       gpio->par_cs |= GPIO_PAR_CS5;
        fbcs->csar5 = CFG_CS5_BASE;
        fbcs->cscr5 = CFG_CS5_CTRL;
        fbcs->csmr5 = CFG_CS5_MASK;
 #endif
 
+#ifdef CONFIG_FSL_I2C
+       gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
+#endif
+
        icache_enable();
 }
 
@@ -124,3 +119,23 @@ int cpu_init_r(void)
 {
        return (0);
 }
+
+void uart_port_conf(void)
+{
+       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+       /* Setup Ports: */
+       switch (CFG_UART_PORT) {
+       case 0:
+               gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
+               break;
+       case 1:
+               gpio->par_uart =
+                   (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
+               break;
+       case 2:
+               gpio->par_timer &= 0x0F;
+               gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
+               break;
+       }
+}