Merge branch 'cleanups' into next

[oweals/u-boot.git] / cpu / mcf52x2 / speed.c

diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c
index 5fafcd8c5f90eaf7748d07efd5685fa686ba2dee..c93a5180eb5702f3e84928dc7ad07a6d60eca056 100644 (file)
--- a/cpu/mcf52x2/speed.c
+++ b/cpu/mcf52x2/speed.c
@@ -39,11 +39,11 @@ int get_clocks (void)
        volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
        unsigned long pllcr;
 
-#ifndef CFG_PLL_BYPASS
+#ifndef CONFIG_SYS_PLL_BYPASS
 
 #ifdef CONFIG_M5249
        /* Setup the PLL to run at the specified speed */
-#ifdef CFG_FAST_CLK
+#ifdef CONFIG_SYS_FAST_CLK
        pllcr = 0x925a3100;     /* ~140MHz clock (PLL bypass = 0) */
 #else
        pllcr = 0x135a4140;     /* ~72MHz clock (PLL bypass = 0) */
@@ -51,7 +51,7 @@ int get_clocks (void)
 #endif                         /* CONFIG_M5249 */
 
 #ifdef CONFIG_M5253
-       pllcr = CFG_PLLCR;
+       pllcr = CONFIG_SYS_PLLCR;
 #endif                         /* CONFIG_M5253 */
 
        cpll = cpll & 0xfffffffe;       /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
@@ -60,7 +60,7 @@ int get_clocks (void)
        pllcr ^= 0x00000001;    /* Set pll bypass to 1 */
        mbar2_writeLong(MCFSIM_PLLCR, pllcr);   /* Start locking (pll bypass = 1) */
        udelay(0x20);           /* Wait for a lock ... */
-#endif                         /* #ifndef CFG_PLL_BYPASS */
+#endif                         /* #ifndef CONFIG_SYS_PLL_BYPASS */
 
 #endif                         /* CONFIG_M5249 || CONFIG_M5253 */
 
@@ -69,18 +69,27 @@ int get_clocks (void)
 
        /* Setup PLL */
        pll->syncr = 0x01080000;
-       while (!(pll->synsr & FMPLL_SYNSR_LOCK)
+       while (!(pll->synsr & FMPLL_SYNSR_LOCK))
                ;
        pll->syncr = 0x01000000;
        while (!(pll->synsr & FMPLL_SYNSR_LOCK))
                ;
 #endif
 
-       gd->cpu_clk = CFG_CLK;
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
+       gd->cpu_clk = CONFIG_SYS_CLK;
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
+    defined(CONFIG_M5271) || defined(CONFIG_M5275)
        gd->bus_clk = gd->cpu_clk / 2;
 #else
        gd->bus_clk = gd->cpu_clk;
 #endif
+
+#ifdef CONFIG_FSL_I2C
+       gd->i2c1_clk = gd->bus_clk;
+#ifdef CONFIG_SYS_I2C2_OFFSET
+       gd->i2c2_clk = gd->bus_clk;
+#endif
+#endif
+
        return (0);
 }