Adding EP2500 MCF5282 board [PATCH]

[oweals/u-boot.git] / cpu / mcf52x2 / cpu_init.c

diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 18308c8a7ab7e332e6b6386d266dad853c05eaf8..5b06930df808c70e3cdcce4049b55ed0b79ad36d 100644 (file)
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -5,6 +5,8 @@
  * MCF5282 additionals
  * (C) Copyright 2005
  * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
+ * (c) Copyright 2010
+ * Arcturus Networks Inc. <www.arcturusnetworks.com>
  *
  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
@@ -101,6 +103,95 @@ void init_fbcs(void)
 }
 #endif
 
+#if defined(CONFIG_M5208)
+void cpu_init_f(void)
+{
+       volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+
+#ifndef CONFIG_WATCHDOG
+       volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG;
+
+       /* Disable the watchdog if we aren't using it */
+       wdg->cr = 0;
+#endif
+
+       scm1->mpr = 0x77777777;
+       scm1->pacra = 0;
+       scm1->pacrb = 0;
+       scm1->pacrc = 0;
+       scm1->pacrd = 0;
+       scm1->pacre = 0;
+       scm1->pacrf = 0;
+
+       /* FlexBus Chipselect */
+       init_fbcs();
+
+       icache_enable();
+}
+
+/* initialize higher level parts of CPU like timers */
+int cpu_init_r(void)
+{
+       return (0);
+}
+
+void uart_port_conf(void)
+{
+       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+       /* Setup Ports: */
+       switch (CONFIG_SYS_UART_PORT) {
+       case 0:
+               gpio->par_uart &= GPIO_PAR_UART0_MASK;
+               gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+               break;
+       case 1:
+               gpio->par_uart &= GPIO_PAR_UART0_MASK;
+               gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
+               break;
+       case 2:
+#ifdef CONFIG_SYS_UART2_PRI_GPIO
+               gpio->par_timer &=
+                   (GPIO_PAR_TMR_TIN0_MASK | GPIO_PAR_TMR_TIN1_MASK);
+               gpio->par_timer |=
+                   (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
+#endif
+#ifdef CONFIG_SYS_UART2_ALT1_GPIO
+               gpio->par_feci2c &=
+                   (GPIO_PAR_FECI2C_MDC_MASK | GPIO_PAR_FECI2C_MDIO_MASK);
+               gpio->par_feci2c |=
+                   (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
+#endif
+#ifdef CONFIG_SYS_UART2_ALT1_GPIO
+               gpio->par_feci2c &=
+                   (GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
+               gpio->par_feci2c |=
+                   (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
+#endif
+               break;
+       }
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+       if (setclear) {
+               gpio->par_fec |=
+                   GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
+               gpio->par_feci2c |=
+                   GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
+       } else {
+               gpio->par_fec &=
+                   (GPIO_PAR_FEC_7W_MASK & GPIO_PAR_FEC_MII_MASK);
+               gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_MASK;
+       }
+       return 0;
+}
+#endif                         /* CONFIG_CMD_NET */
+#endif                         /* CONFIG_M5208 */
+
 #if defined(CONFIG_M5253)
 /*
  * Breath some life into the CPU...
@@ -131,7 +222,7 @@ void cpu_init_f(void)
        mbar2_writeByte(MCFSIM_INTBASE, 0x40);  /* Base interrupts at 64 */
        mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
 
-       /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); *//* Enable a 1 cycle pre-drive cycle on CS1 */
+       /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
 
        /* FlexBus Chipselect */
        init_fbcs();
@@ -181,9 +272,14 @@ void cpu_init_f(void)
        /* FlexBus Chipselect */
        init_fbcs();
 
+#ifdef CONFIG_SYS_MCF_SYNCR
+       /* Set clockspeed according to board header file */
+       mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
+#else
        /* Set clockspeed to 100MHz */
-       mbar_writeShort(MCF_FMPLL_SYNCR,
+       mbar_writeLong(MCF_FMPLL_SYNCR,
                        MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
+#endif
        while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
 }
 
@@ -219,7 +315,8 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 {
        if (setclear) {
                /* Enable Ethernet pins */
-               mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
+               mbar_writeByte(MCF_GPIO_PAR_FECI2C,
+                              (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));
        } else {
        }
 
@@ -487,6 +584,12 @@ void cpu_init_f(void)
 #ifdef CONFIG_SYS_PTCPAR
        MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
 #endif
+#if defined(CONFIG_SYS_PORTTC)
+       MCFGPIO_PORTTC = CONFIG_SYS_PORTTC;
+#endif
+#if defined(CONFIG_SYS_DDRTC)
+       MCFGPIO_DDRTC  = CONFIG_SYS_DDRTC;
+#endif
 #ifdef CONFIG_SYS_PTDPAR
        MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
 #endif
@@ -494,6 +597,9 @@ void cpu_init_f(void)
        MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
 #endif
 
+#if defined(CONFIG_SYS_DDRD)
+       MCFGPIO_DDRD = CONFIG_SYS_DDRD;
+#endif
 #ifdef CONFIG_SYS_DDRUA
        MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
 #endif