ixp: remove the option to include the Microcode

[oweals/u-boot.git] / cpu / i386 / sc520.c

diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c
index 689e775c938160a7747d2b51f3d1adb37275ad33..12e8f38716f519779b672cbc90ba4b569b748719 100644 (file)
--- a/cpu/i386/sc520.c
+++ b/cpu/i386/sc520.c
@@ -25,17 +25,18 @@
  * but idependent of implementation */
 
 #include <config.h>
-
-#ifdef CONFIG_SC520
-
 #include <common.h>
 #include <config.h>
 #include <pci.h>
-#include <ssi.h>
+#ifdef CONFIG_SC520_SSI
+#include <asm/ic/ssi.h>
+#endif
 #include <asm/io.h>
 #include <asm/pci.h>
 #include <asm/ic/sc520.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * utility functions for boards based on the AMD sc520
  *
@@ -93,8 +94,6 @@ u32 read_mmcr_long(u16 mmcr)
 
 void init_sc520(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        /* Set the UARTxCTL register at it's slower,
         * baud clock giving us a 1.8432 MHz reference
         */
@@ -111,7 +110,7 @@ void init_sc520(void)
        write_mmcr_word(SC520_HBCTL,0x04);      /* enable posted-writes */
 
 
-       if (CFG_SC520_HIGH_SPEED) {
+       if (CONFIG_SYS_SC520_HIGH_SPEED) {
                write_mmcr_byte(SC520_CPUCTL, 0x2);     /* set it to 133 MHz and write back */
                gd->cpu_clk = 133000000;
                printf("## CPU Speed set to 133MHz\n");
@@ -139,17 +138,24 @@ void init_sc520(void)
 
 unsigned long init_sc520_dram(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        bd_t *bd = gd->bd;
 
        u32 dram_present=0;
        u32 dram_ctrl;
-
+#ifdef CONFIG_SYS_SDRAM_DRCTMCTL
+       /* these memory control registers are set up in the assember part,
+        * in sc520_asm.S, during 'mem_init'.  If we muck with them here,
+        * after we are running a stack in RAM, we have troubles.  Besides,
+        * these refresh and delay values are better ? simply specified
+        * outright in the include/configs/{cfg} file since the HW designer
+        * simply dictates it.
+        */
+#else
        int val;
 
-       int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY;
-       int refresh_rate        = CFG_SDRAM_REFRESH_RATE;
-       int ras_cas_delay       = CFG_SDRAM_RAS_CAS_DELAY;
+       int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY;
+       int refresh_rate        = CONFIG_SYS_SDRAM_REFRESH_RATE;
+       int ras_cas_delay       = CONFIG_SYS_SDRAM_RAS_CAS_DELAY;
 
        /* set SDRAM speed here */
 
@@ -163,6 +169,7 @@ unsigned long init_sc520_dram(void)
        } else {
                val = 3;  /* 62.4us */
        }
+
        write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
 
        val = read_mmcr_byte(SC520_DRCTMCTL);
@@ -182,13 +189,12 @@ unsigned long init_sc520_dram(void)
                val |= 1;
        }
        write_mmcr_byte(SC520_DRCTMCTL, val);
-
+#endif
 
        /* We read-back the configuration of the dram
         * controller that the assembly code wrote */
        dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
 
-
        bd->bi_dram[0].start = 0;
        if (dram_ctrl & 0x80) {
                /* bank 0 enabled */
@@ -275,7 +281,7 @@ int pci_sc520_set_irq(int pci_pin, int irq)
 {
        int i;
 
-# if 0
+# if 1
        printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
 #endif
        if (irq < 0 || irq > 15) {
@@ -384,7 +390,7 @@ void pci_sc520_init(struct pci_controller *hose)
 
 #endif
 
-#ifdef CFG_TIMER_SC520
+#ifdef CONFIG_SYS_TIMER_SC520
 
 
 void reset_timer(void)
@@ -397,7 +403,7 @@ void reset_timer(void)
 ulong get_timer(ulong base)
 {
        /* fixme: 30 or 33 */
-       return  read_mmcr_word(SC520_GPTMR0CNT) / 33;
+       return  read_mmcr_word(SC520_GPTMR0CNT) / 33;
 }
 
 void set_timer(ulong t)
@@ -498,4 +504,13 @@ u8 ssi_rx_byte(void)
        return read_mmcr_byte(SC520_SSIRCV);
 }
 
-#endif /* CONFIG_SC520 */
+#ifdef CONFIG_SYS_RESET_SC520
+void reset_cpu(ulong addr)
+{
+       printf("Resetting using SC520 MMCR\n");
+       /* Write a '1' to the SYS_RST of the RESCFG MMCR */
+       write_mmcr_word(SC520_RESCFG, 0x0001);
+
+       /* NOTREACHED */
+}
+#endif