Merge commit 'u-boot/master' into for-1.3.1

[oweals/u-boot.git] / cpu / bf533 / start.S

diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S
index 8e2d725af2cdba11346fbda73519b37ff2e95e25..67a60cf21e00f41c085a37ae5643af5b893bae51 100644 (file)
--- a/cpu/bf533/start.S
+++ b/cpu/bf533/start.S
@@ -1,7 +1,7 @@
 /*
  * U-boot - start.S Startup file of u-boot for BF533/BF561
  *
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Devices Inc.
  *
  * This file is based on head.S
  * Copyright (c) 2003  Metrowerks/Motorola
@@ -26,13 +26,13 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
  */
 
 /*
  * Note: A change in this file subsequently requires a change in
- *       board/$(board_name)/config.mk for a valid u-boot.bin 
+ *       board/$(board_name)/config.mk for a valid u-boot.bin
  */
 
 #define ASSEMBLY
@@ -82,7 +82,7 @@ _stext:
        SSYNC;
 
        /* As per HW reference manual DAG registers,
-        * DATA and Address resgister shall be zero'd 
+        * DATA and Address resgister shall be zero'd
         * in initialization, after a reset state
         */
        r1 = 0; /* Data registers zero'd */
@@ -99,7 +99,7 @@ _stext:
        p3 = 0;
        p4 = 0;
        p5 = 0;
-       
+
        i0 = 0; /* DAG Registers zero'd */
        i1 = 0;
        i2 = 0;
@@ -150,12 +150,12 @@ no_soft_reset:
        r1 = 0;
        LSETUP(4,4) lc0 = p1;
        [ p0 ++ ] = r1;
-       
+
        p0.h = hi(SIC_IWR);
-        p0.l = lo(SIC_IWR);
-        r0.l = 0x1;
-        w[p0] = r0.l;
-        SSYNC;
+       p0.l = lo(SIC_IWR);
+       r0.l = 0x1;
+       w[p0] = r0.l;
+       SSYNC;
 
        sp.l = (0xffb01000 & 0xFFFF);
        sp.h = (0xffb01000 >> 16);
@@ -259,8 +259,8 @@ DMA:
        /* Set Destination DMAConfig = DMA Enable,
        Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
        W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
-       
-WAIT_DMA_DONE: 
+
+WAIT_DMA_DONE:
        p0.h = hi(MDMA_D0_IRQ_STATUS);
        p0.l = lo(MDMA_D0_IRQ_STATUS);
        R0 = W[P0](Z);